Trw Limited

Northrop Grumman Systems Corporation

Lynn A Abelson

George L Kerber

Raffi N Elmadjian

Eric G Ladizinsky

Quentin P Herr

The self inductance associated with a capacitance A in a superconductor integrated circuit (FIG. ) is reduced by adding a layer of superconductor metal (A ) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (&ldquo;SFQ&rdquo;) pulse through the capacitor. Capacitors ( and FIG. ) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. ) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current ( ) may be supplied to multiple SQUIDs ( & & FIG. ) serially, reducing the supply current required previously for operation of multiple SQUIDs.

Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits

A high-temperature (10 K) superconductive integrated circuit has a ground plane (,), an interlevel dielectric (,), and a low value resistor (,) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (,) connected between interconnect wires (,) to produce a desired resistance with a short distance between the interconnect wires (,), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (,) on the ground plane (,) in separate steps, depositing and etching the trilayer (,), etching the low value resistor (,) on the dielectric (,), depositing the high value resistor (,) at substantially the same level above the ground plane (,) as the interconnect wires (,) of the first wire layer (,), and etching the interconnect wires (,) of the second wire layer (,) on the high value resistor (,).

Low inductance superconductive integrated circuit and method of fabricating the same

A high-temperature (10 K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).

Low inductance superconductive integrated circuit and method of

A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).

Growing community of inventors

Rancho Palos Verdes, CA, United States of America

Lynn A Abelson