International Business Machines Corporation

Globalfoundries Inc.

Lyndon Ronald Logan

Edward J Nowak

Robert Russell Robison

Louis L Hsu

James Albert Slinkman

Chang-Ming Hsieh

Jonathan K Winslow, Ii

Jack Allan Mandelman

Andres Bryant

James William Adkisson

Seiki Ogura

Michael John Hargrove

Isabel Ying Yang

Jonathan K Winslow

Yan He

A source/drain epitaxial electrical monitor and methods of characterizing epitaxial growth through capacitance measurements are provided. The structure includes a plurality of fin structures; one or more gate structures, perpendicular to and intersecting the plurality of fin structures. The structure further includes a first connection by a first contact at one fin-end of every other fin structure of the plurality of fin structures, and a second connection by a second contact at one end of an alternate fin structure of the plurality of fin structures.

Source/drain epitaxial electrical monitor

Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.

Capacitive measurements of divots in semiconductor devices

Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented method of determining a laterally diffuse dopant profile in semiconductor structures by providing first and second semiconductor structures having plurality of gate array structures in a silicided region separated from each other by a first distance and second distance. A potential difference is applied across the plurality of gate array structures and resistances are determined. A linear-regression fit is performed on measured resistance versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures based on a semiconductor device model.

Extraction of resistance associated with laterally diffused dopant profiles in CMOS devices

Structures and methods of manufacturing a fin-type PIN diode array include forming a plurality of first charge-type doped silicon fins disposed in parallel on a planar substrate in a first direction, forming undoped epitaxial growths of silicon at intervals along a length of each silicon fin, where each epitaxial growth includes a depleted intrinsic region, and forming a plurality of second charge-type doped polysilicon fins disposed in parallel and disposed perpendicularly to the first direction. The polysilicon fins are formed to contact, at intervals along a length of each polysilicon fin, an uppermost surface of one of the undoped epitaxial growths of silicon, to form a PIN diode at each intersection of each of the first charge-type doped silicon fins and the second charge-type doped polysilicon fins.

Fin-type PIN diode array

Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.

ZRAM heterochannel memory

A plurality of diode/resistor devices are formed within an integrated circuit structure using manufacturing equipment operatively connected to a computerized machine. Each of the diode/resistor devices comprises a diode device and a resistor device integrated into a single structure. The resistance of each of the diode/resistor devices is measured during testing of the integrated circuit structure using testing equipment operatively connected to the computerized machine. The current through each of the diode/resistor devices is also measured during testing of the integrated circuit structure using the testing equipment. Then, response curves for the resistance and the current are computed as a function of variations of characteristics of transistor devices within the integrated circuit structure and/or variations of manufacturing processes of the transistor devices within the integrated circuit structure.

Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations

A diagnostic method of and computer system for root-cause analysis of performance variations of FETs in integrated circuits and a method and computer system for monitoring a field effect transistor manufacturing process. The diagnostic method includes measuring source currents in the linear and saturated regions of two FETs, calculating ratios of the source currents in the linear and saturated regions for the and two FETs and comparing the ratios of the two FETs to determine a probable root cause for a performance variation between the two FETs. One of the FETs has a known good performance.

Diagnostic method for root-cause analysis of FET performance variation

A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and align to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the P-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

Method and structure to reduce CMOS inter-well leakage

High performance asymmetric transistors including controllable diode characteristics at the source and/or drain are developed by supplying impurities with high accuracy of location by angled implants in a trench or diffusion from a solid body formed as a sidewall of doped material. High concentration gradient of impurities to support high performance is achieved by providing for reduced heat treatment after the impurity is supplied in order to limit diffusion previously necessary to achieve the desired location of impurity structures. Damascene or quasi-Damascene gate structures are also provided for high dimensional uniformity, increased manufacturing yield and structural integrity of the transistor.

Method of controlling floating body effects in an asymmetrical SOI device

A method of forming a semiconductor device with improved leakage control, includes: providing a semiconductor substrate; forming a trench in the substrate; forming a leakage stop implant in the substrate under the bottom of the trench and under and aligned to a sidewall of the trench; filling the trench with an insulator; and forming an N-well (or a P-well) in the substrate adjacent to and in contact with an opposite sidewall of the trench, the N-well (or the N-well) extending under the trench and forming an upper portion of an isolation junction with the leakage stop implant, the upper portion of the isolation junction located entirely under the trench. The leakage control implant is self-aligned to the trench sidewalls.

A field effect transistor (FET) device, which mitigates leakage current induced along the edges of the FET device, is isolated by shallow trench isolation having a channel width between a first and a second shallow trench at a first and second shallow trench edges. A gate extends across the channel width between the first and second shallow trenches. The gate has a first length at the shallow trench edges and a second length less than the first length between the shallow trench edges. The first length and the second length are related such that the threshold voltage, V.sub.t, at the shallow trench edges is substantially equal to V.sub.t between the shallow trench edges. The gate structure of the FET device is produced using a unique phase shift mask that allows the manufacture of submicron FET devices with very small channel lengths.

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Poughkeepsie, NY, United States of America

Lyndon Ronald Logan