International Business Machines Corporation

Lyle Edwin Grosbach

David John Krolak

Glen Howard Handlogten

James Francis Mikos

David Alan Norgaard

Peder James Paulson

John David Irish

Kent Harold Haselhorst

James Anthony Marcella

Robert Allen Drehmel

Herman Lee Blackmon

Quentin G Schmierer

Daniel Frank Moertl

Adrian Cuenin Gerhard

Sheldon Bernard Levenstein

Donald Lee Freerksen

Farnaz Mounes-Toussi

David W Marquart

A method and controller for implementing storage adapter performance optimization with chained hardware operations completion coalescence, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines, and a processor. A plurality of the command blocks are selectively arranged by firmware in a predefined chain including a plurality of simultaneous command blocks. All of the simultaneous command blocks are completed in any order by respective hardware engines, then the next command block in the predefined chain is started under hardware control without any hardware-firmware (HW-FW) interlocking with the simultaneous command block completion coalescence.

Implementing storage adapter performance optimization with hardware operations completion coalescence

A method and apparatus are provided for implementing hierarchical scheduling of oversubscribed virtual paths with underutilized bandwidth that works for both ATM (cell) and IP (frame) scheduling. A scheduler includes a first calendar for pipes and autonomous flows and a second calendar for pipe flows. A winner of a pipe or an autonomous flow is identified from the first calendar. Responsive to an identified winner pipe, a pipe queue is checked for an associated pipe flow for the winner pipe. Responsive to identifying an empty pipe queue for the winner pipe, a pipe win credit is assigned to the pipe without reattaching the winner pipe to the first calendar. Then a next winner is identified from the first calendar. When a winner pipe flow is identified from the second calendar and the pipe win credit is assigned to the pipe for the winner pipe flow, then the winner pipe flow is serviced without delay.

Method and apparatus for hierarchial scheduling of virtual paths with underutilized bandwidth

A method and programmable oscillator model are provided for implementing high frequency clock generation for a simulation environment. The programmable oscillator model includes an internal ring oscillator for generating a high frequency clock. The internal ring oscillator counts a number of clocks and determines when to switch the reference clock. For example, a clock edge time is recorded as a two-byte field, where a high byte records a programmable number of fast clocks per clock edge, and a low byte records a fraction of a clock edge. Each time the reference clock switches a count down counter is loaded with the high byte, and the low byte is added to the current fraction. If the fraction has a carry, an additional fast clock is added to the count down counter.

Programmable oscillators for high frequency clock generation for simulation environments

In a first aspect, a method is provided for scheduling connections for a network processor. The method includes the steps of, in a cache, scheduling a plurality of connections to be serviced based on quality of service parameters stored in a control structure corresponding to each connection and during a scheduling opportunity (1) identifying one or more of the plurality of connections in the cache to be serviced; (2) selecting one of the connections identified to be serviced; (3) servicing the selected connection; (4) accessing one or more portions of the control structure in the cache; (5) calculating a next service time when the selected connection is to be serviced; and (6) determining whether to schedule the selected connection to be serviced in one of the cache and a calendar based on the next service time. Numerous other aspects are provided.

High-speed scheduler

A shared bus non-sequential data ordering method and apparatus are provided. A maximum bus width value and a minimum transfer value are identified. A minimum number of sub-transfers is identified responsive to the identified maximum bus width value and the minimum transfer value. A bus unit having a maximum number of chips to receive and/or send data receives data in a predefined order during multiple sub-transfers. During each data sub-transfer, a corresponding predefined word is transferred to each chip of the bus unit.

Shared bus non-sequential data ordering method and apparatus

A method and apparatus for handling commands and data associated therewith includes a data buffer and a command directory. The command directory receives and stores a command from at least one command source, and freely allocates an unused portion of the data buffer to the command. The data buffer stores the data associated with the command in the allocated portion of the data buffer. Based on status information also stored by the command directory with respect to each command, routing logic in the command directory, corresponding to each command sink, identifies which commands stored in the command buffer to route to the command sink, and routes the identified commands to the command sink. The routing logic also determines a priority of the identified commands and routes the identified commands in order of priority. The command directory also uses the status information to track the processing of commands.

Multi-entry fully associative transition cache

A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.

Abridged virtual address cache directory

The ability to harmonize the activities of individual computer system components with control signals is key to the operation of any computer system. Examples of this need for control include the need to write data to multiple registers on the same clock cycle, the need to clear values on multiple entities on the same clock cycle, and the need to stop and start the master clock pulse train itself. In the past, providing this control was not a problem because control signals could be reliably sent to all the timing dependent components within a single cycle of the master clock pulse train. This control methodology is called 'single cycle control.' Today, however, single cycle control is not trustworthy in all situations. Master clock pulse trains are so fast that single cycle control is no longer reliable when timing dependent components reside in locations distant from the control signal generating circuitry. The present invention provides reliable control in all cases, including the situation where a master clock pulse train is so fast that single cycle control is not viable.

Growing community of inventors

Rochester, MN, United States of America

Lyle Edwin Grosbach