Qualcomm Incorporated

Toshiba America Electronic Components, Inc.

Tality, L.p.

Cadence Design Systems, Inc.

Unisys Corporation

Cadenca Design Systems, Inc.

Luverne Ray Peterson

Thomas Clark Bryan

Alvin Leng Sun Loke

Tin Tin Wee

Stephen Knol

Gregory Lynch

Jacob Schneider

Reza Jalilizeinali

Yue Li

Stephen Thilenius

Mohammed Mizanur Rahman

Sreeker Dundigal

Kenneth Dubowski

Jonathan A Levi

Alvin Loke

Roger Mar

Paul Abelovski

James R Welch

Gregory Francis Lynch

Stephen Robert Knol

A semiconductor die including: a die-to-die interface including an input/output (I/O) circuitry area and an electrical contact area; wherein the electrical contact area includes an array of electrical contacts disposed on a side of the semiconductor die; and wherein the I/O circuitry area includes a plurality of drivers, each of the drivers coupled to at least one electrical contact in the electrical contact area, and a plurality of electrostatic discharge (ESD) protection devices, each of the ESD protection devices coupled to a respective driver, further wherein the I/O circuitry area and the electrical contact area are separated in a top-down view of the semiconductor die.

Die-to-die interface configuration and methods of use thereof

Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receivesdata bits during operation would havetransceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

Systems and methods for wafer-level loopback test

A die-to-die data transmitter is disclosed with a pull-up one-shot circuit and a pull-down one-shot circuit, each forming a delay circuit that determines a variable preemphasis period.

Delay line for one shot pre-emphasis

Circuits and methods for loopback testing are provided. A die incorporates a receiver (RX) to each transmitter (TX) as well as a TX to each RX. This architecture is applied to each bit so, e.g., a die that transmits or receives 32 data bits during operation would have 32 transceivers (one for each bit). Focusing on one of the transceivers, a loopback architecture includes a TX data path and an RX data path that are coupled to each other through an external contact, such as a via at the transceiver. The die further includes a transmit clock tree feeding the TX data path and a receive clock tree feeding the RX data path. The transmit clock tree feeds the receive clock tree through a conductive clock node that is exposed on a surface of the die. Some systems further include a variable delay in the clock path.

A transmitter is disclosed with a pull-up feedback circuit and a feedback circuit. The transmitter includes an output driver for driving an output terminal.

Transmitter with feedback terminated preemphasis

A programmable equalizer and related method are provided. The equalizer includes a pair of current-setting field effect transistors (FETs) coupled in series with a pair of input FETs and a pair of load resistors, respectively, between a first voltage rail (Vdd) and a second voltage rail (ground). A programmable equalization circuit is coupled between the sources of the input FETs, comprising a plurality of selectable resistive paths and a variable capacitor, which could also be configured as a plurality of selectable capacitive paths. Each of the selectable resistive paths (as well as each of the selectable capacitive paths) include a selection FET for selectively coupling the corresponding resistive (or capacitive) path between the sources of the input FETs. In the case where one of the input FETs is biased with a reference gate voltage, the source of each selection FET is coupled to the source of such input FET.

Programmable high-speed equalizer and related method

A circuit includes a data input in communication with a first transistor stack; a first capacitor having a first capacitance and in communication with a power supply via a first transistor of the first transistor stack, wherein the first transistor is configured to charge the first capacitor in response to the data input receiving a signal corresponding to a first binary value; a data output node coupled between the first transistor stack and a transmission line having a second capacitance; and wherein the first capacitor is coupled between the data output node and a second transistor of the first transistor stack, further wherein the second transistor is configured to discharge the first capacitor to the data output node in response to the data input receiving a signal corresponding to a second binary value.

Systems and methods to provide charge sharing at a transmit buffer circuit

Circuits for die-to-die clock distribution are provided. A system includes a transmit clock tree on a first die and a receive clock tree on a second die. The transmit clock tree and the receive clock tree are the same, or very nearly the same, so that the insertion delay for a given bit on the transmit clock tree is the same as an insertion delay for a bit corresponding to the given bit on the receive clock tree. While there may be clock skew from bit-to-bit within the same clock tree, corresponding bits on the different die experience the same clock insertion delays.

Systems and methods for clock distribution in a die-to-die interface

Methods, systems, and circuits for providing reception and capture of data using a mismatched impedance and an equalizer to save power are disclosed. A data receiver in communication with a transmission line, the data receiver having a termination impedance that is mismatched with respect to a characteristic impedance of the transmission line; and an equalizer in communication with the data receiver, the equalizer configured to receive a channel-transmitted data signal from the data receiver and to re-shape the signal to reduce distortion RC attenuation; wherein the circuit is configured to selectably operate in a first mode wherein the termination impedance is matched with respect to the characteristic impedance of the transmission line and a second mode wherein the termination impedance is mismatched with respect to the characteristic impedance of the transmission line and the signal is not recoverable but for the equalizer.

Circuits and methods providing high-speed data link with equalizer

An input receiver is provided with a pass transistor that is controlled to pass an input signal to an inverter only while a first binary state for the input signal equals a low voltage. The input receiver also includes a source follower transistor configured to pass a threshold-voltage-reduced version of the input signal while the first binary state of the input signal equals a high voltage greater than the low voltage.

Low power receiver with wide input voltage range

A circuit includes a first die having a first array of exposed data nodes, and a second die having a second array of exposed data nodes, wherein a given data node of the first array corresponds to a respective data node on the second array, further wherein the first array and the second array share a spatial arrangement of the data nodes, wherein the first die has data inputs and sequential logic circuits for each of the data nodes of the first array on a first side of the first array, and wherein the second die has data outputs and sequential logic circuits for each of the data nodes of the second array on a second side of the second array, the first and second sides being different.

Systems and methods for providing data channels at a die-to-die interface

A temperature sensor generates a digital output signal representative of the absolute temperature of the sensor. The sensor includes a first circuit configured to generate a complementary to absolute temperature (CTAT) voltage signal and a second circuit configured to generate a proportional to absolute temperature (PTAT) current signal. A comparator receives the CTAT and PTAT signals and generates a comparison signal based on a comparison between the signals. A converter circuit receives the comparison signal and generates a digital output signal based on the comparison signal. The digital output signal is representative of the temperature of the sensor.

Digital output temperature sensor and method of temperature sensing

Digital output temperature sensor

A non-inverting AC/DC input buffer combines the desirable characteristics of an alternating current (AC) input buffer including low delay, high speed, and high input voltage swing range with the desirable characteristics of a direct current (DC) input buffer including stability, reliability, and 'automatic' high and low data setup. The AC/DC buffer includes logic to help prevent the DC input buffer from interfering with the AC input buffer until the DC input buffer has completed its operations on a transitioning input. The DC buffer is configured to enable the AC buffer to process low input voltage swings such as, for example, voltage swings less than the difference in power supply voltages.

Growing community of inventors

San Diego, CA, United States of America

Luverne Ray Peterson