Unisys Corporation

Burroughs, Inc.

Tality, L.p.

LuVerne R Peterson

Laurence P Flora

Mohamed I Elmasry

Cevat Kumbasar

David W Page

Stephen J Chung Chan

Michael A Rehart

A CAM cell design methodology and a method of pre-charge and comparison timing is disclosed. A CAM cell utilizing this design methodology includes grounding circuitry and a P-channel transistor configured to communicate a comparison result to a match line using the Miller effect. In one embodiment, the CAM cell further includes a positive comparison bit line, a negative comparison bit line, a first dual-ended CAM memory core cell configured to store data, a second dual-ended CAM memory core cell configured to store masking data, comparison circuitry, and a second P-channel transistor configured to communicate a masked state to the match line.

Content addressable memory cell and design methodology utilizing grounding circuitry

An electronic control module reduces ringing in the digital signals on a transmission line which has multiple transmitters, receivers, and parasitic inductors and capacitors coupled to the line. Preferably, a copy of this control module is provided at each node on the line which has a transmitter and/or receiver. Each copy of the control module has three main parts--a sensing circuit, a pulse generating circuit, and a switching circuit. The sensing circuit is coupled to the transmission line, and it generates a control signal when the digital signal on the transmission line changes from a low voltage to a high voltage. The pulse generating circuit receives the control signal and responds by generating a single pulse. The switching circuit receives the pulse and, in response, couples a high supply voltage to the transmission line while the pulse occurs.

Control module for reducing ringing in digital signals on a transmission

A random access compare array, on an integrated circuit chip is comprised of a plurality of multi-bit comparator circuits. Each comparator circuit is coupled to a respective multi-bit register; and, each comparator circuit is also coupled to an address distribution circuit which receives a compare address and sends the compare address to all of the comparator circuits. A respective match signal is generated by each comparator circuit which indicates when the compare address and the content of the register that is coupled to the comparator are equal. Also, operating in parallel with the generation of the match signals is a match selection circuit which receives a select address and in response passes one match signal to a single output pin. Due to the parallel operation of the compare-select circuits, the speed of operation is greatly increased; and due to the selective passing of any of the match signals to a single output pin, the size of the array is not pin limited.

Random access compare array

A digital adder module has a carry-in terminal, N pairs of data terminals, N sum terminals, and a carry-out terminal. A high-speed low-capacitance carry bypass signal path couples the carry-in terminal to the carry-out terminal. In one preferred embodiment, the capacitance of the bypass path is due solely to one transistor channel plus one transistor drain plus one internal logic gate plus interconnections between them.

Digital adder having a high-speed low-capacitance carry bypass signal

A digital translator, on a semiconductor chip that contains N-channel transistors and P-channel transistors which have threshold voltages that vary about respective nominal values, includes an input/output module which is made of the transistors and which receives a digital input signal at two voltage levels and in response generates a digital output signal at two different voltage levels. To compensate for the threshold variations and thereby stabilize the voltage levels of the output signal, the translator also includes a voltage generator which produces a reference voltage for the input/output module. This generator is made of the N-channel transistors and the P-channel transistors, and it varies the reference voltage in proportion to the threshold voltage of the N-channel transistors regardless of how the threshold voltage of the P-channel transistors varies; and, the input/output module includes one of the N-channel transistors which receives the reference voltage and produces the output signal by conducting in proportion to the reference voltage only when the input signal is at one of its two voltage levels.

Digital signal translator having compensation for P-channel and

A multiplier circuit is comprised of multiple arrays of logic cells. Each array has input lines for receiving two multibit binary numbers that are to be multiplied together; and each logic cell includes an AND gate for producing single power product terms by multiplying together one bit from each of the two numbers. These cells are arranged in the arrays such that the total quantity of single power product terms of any particular power in the respective arrays is within 30% of each other. One subset of cells of each array also includes a respective two-bit adder, and another subset of cells of each array includes a respective three-bit adder. These two-bit and three-bit adders are interconnected within each array to form an intermediate result, in parallel with the other arrays, which consists of a partial sum of all product terms in the array together with no more than one remaining carry-in for each bit of that partial sum. All of these intermediate results are then added by parallel input adders to produce the product of the two numbers.

Fast multiplier circuit incorporating parallel arrays of two-bit and

An error-correcting memory system includes a storage module which receives an address during a read cycle and which reads data bits and check bits at the address, and it further includes a low DC power logic circuit which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the logic circuit is comprised of: a plurality of logic gates, one for generating each of the minterms by passing a constant power dissipating current to selectively decode the check bits; a control circuit for generating a control signal that is in one state during only a small fraction of the read cycle and is otherwise in an opposite state; and an enabling circuit, coupled between the control circuit and the logic gates, for enabling their selective decoding by permitting the constant current to flow through the gates only while the control signal is in its one state.

Memory system employing a low DC power gate array for error correction

An error-correcting memory system includes a storage module which receives an address and which reads data bits and check bits at the address, and it further includes a zero DC power gate array which corrects errors in the data bits by decoding multiple minterms from the check bits; wherein the gate array is comprised of: a plurality of capacitors, one for each of the minterms; a control circuit for generating a control signal that is in one state when the minterms are to be detected and is otherwise in an opposite state; a charging circuit, coupled between the control circuit and the capacitors, for charging all of the capacitors only when the control signal is in its opposite state; and a discharging circuit, coupled between the control circuit and the capacitors, for indicating the presence of the minterms by selectively discharging the capacitors as a selectable decode of the check bits only when the control signal is in its one state.

Memory system employing a zero DC power gate array for error correction

A magnetic bubble memory (of the type that has a magnetic film, a plurality of magnetic bubbles in the film, and an insulating layer over the film) includes an improved electromagnetic structure on the insulating layer for stretching the bubbles to aid in their detection; which structure is comprised of a plurality of elongated permalloy elements on the insulator and arranged in spaced apart rows with only one of the elements per row; each element has a pattern that is X-shaped which repeats along the element in the direction of elongation; the X in the pattern has two short legs and two long legs; and the pattern is repeated such that the short legs of one X join with the long legs of the next X.

High-speed, compact magnetic bubble stretcher

A magnetic bubble memory includes a planar magnetic film containing a plurality of magnetic bubbles which move in response to a magnetic field that rotates the film's plane; and further includes an improved mechanism for detecting the bubbles comprised of: a pair of elongated magnetoresistive members that lie over the film alongside of one another; the members having fingers that extend towards each other along the direction of elongation; the fingers of one member being interdigitated with the fingers of the other member such that they mesh together but do not touch; the fingers being interdigitated at angles of less than 180.degree. so that magnetic poles which attract the bubbles are sequentially induced in the fingers of only one member, in the fingers of both members, and in the fingers of only the other member by each rotation of the field.

Detector-dummy detector combination which is integrated as a single

This disclosure relates to a programmable logic array having an AND array disposed for receiving n input signals, an OR array providing k output signals on k output lines and m term lines coupling the AND and OR arrays together. New and improved AND and OR arrays are disclosed wherein the AND array includes n X m cells and each cell has first and second transistor means coupled in series between one of the term lines and a reference potential. Each cell includes a storage element that has an output terminal coupled to the control element of the first transistor means and one of the n input terminals is coupled to the control element of the second transistor means. The OR array includes m X k cells wherein each cell has third and fourth transistor means coupled in series between one of said output lines and a reference potential. Each of the OR array cells also includes a storage element having an output terminal coupled to the control element of the third transistor and one of the m term lines is coupled to the control element of the fourth transistor.

Re-programmable PLA

Disclosed is an improved static memory cell comprised of first and second conductive means for carrying respective bias voltages in the cell, a third conductive means for carrying an input/output voltage signal in the cell, and a Lambda diode coupled between the first and third conductive means for there providing a negative dynamic resistance whenever the input/output voltage signal is within a predetermined range between the bias voltages on the first and second conductive means, with the improvement being a voltage dependent resistance means coupled between the second and third conductive means for there providing a negative dynamic resistance in response to at least some of the input/output voltages within said range.

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San Diego, CA, United States of America

LuVerne R Peterson