National Semiconductor Corporation

Texas Instruments Corporation

University of California

Luu Thanh Nguyen

William Paul Mazotti

Peter Deane

Bruce Carlton Roberts

Ken Pham

Jia Liu

Anindya Poddar

Ashok S Prabhu

Hau Thanh Nguyen

Hem P Takiar

John P Briant

Yi Yan

Stephen Gee

Nikhil Vishwanath Kelkar

Michael R Nelson

Janet E Townsend

Roger William Clarke

Christopher James Smith

Jitendra Mohan

Makoto Shibuya

Haryanto Chandra

Brian Huss

Todd Thyes

Randall Walberg

John Rukavina

Glenn Woodhouse

Shahram Mostafazadeh

Matthew David Romig

Yongseon Koh

Genki Yano

Makoto Yoshino

Shoichi Iriguchi

James Cooper Wainerdi

Noboru Nakanishi

Hiroyuki Sada

Neeraj Anil Pendse

Dibyajat Mishra

Tomoko Noguchi

Cade Murray

Alexander Harvey Scheuermann

Chen-Hui Tsay

Mutsumi Masumoto

Ranjan J Mathew

Woochan Kim

Joseph O Smith

James B Wieser

Kengo Aoya

Viraj Ajit Patwardhan

Masamitsu Matsuura

Alan Erik Segervall

Peng-Cheng Lin

Mahmud Halim Chowdhury

Daiki Komatsu

Artur Darbinyan

Kenneth D Pedrotti

Jacob Adams Wysocki

Christopher G Quentin

Vijaylaxmi Gumaste

Jie Mao

Robert Dahlgren

Stephen Jacob

Ethan Warner

Arnold Smith

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Bump bond structure for enhanced electromigration performance

An electronic device () includes a substrate () and an integrated circuit () provided on the substrate () having a surface facing away from the substrate (). An insulating layer () extends over the substrate () and around the integrated circuit () to define an interface () between the insulating layer () and the integrated circuit (). An electrically conductive via () is provided on the surface of the integrated circuit (). An insulating material () extends over the via () and includes an opening () exposing a portion of the via (). A repassivation member () extends over the insulating layer () and has a surface () aligned with the interface (). An electrically conductive redistribution member () is electrically connected to the via () and extends over the repassivation member () into contact with the insulating layer ().

Fan-out electronic device

A method for backside metallization includes inkjet printing a pattern of nanosilver conductive ink on a first surface of a silicon wafer. The silicon wafer includes a plurality of dies. The pattern includes a clearance area along a scribe line between the dies. A laser is focused, through a second surface of the wafer, at a point between the first surface of the silicon wafer and the second surface of the silicon wafer. The second surface is opposite the first surface. The dies are separated along the scribe line.

Integrated circuit backside metallization

In one aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package includes a lead frame. A semiconductor die is attached to a first side of the lead frame. A protective shell covers at least a first portion of the first surface of the semiconductor die. The protective shell comprises of ink residue. A layer of molding compound covers an outer surface of the protective shell and exposed portion of the first surface of the semiconductor die. A cavity space is within an inner space of the protective shell and the first portion of the top surface of the semiconductor die.

3D-printed protective shell structures with support columns for stress sensitive circuits

In a described example, a packaged semiconductor device includes: a semiconductor die with a component proximate to a surface of the semiconductor die; the semiconductor die mounted on a substrate. The component is covered with a first polymer layer with a first modulus and at least a portion of the first polymer layer is covered by at least one second polymer layer with a second modulus and the second modulus is greater than the first modulus. The semiconductor die and a portion of the substrate are covered with mold compound.

Packaged semiconductor device with multilayer stress buffer

In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 &#x3bc;m on a surface of the copper corrosion inhibitor layer.

Copper passivation

Apparatus to form a transformer, an inductor, a capacitor or other passive electronic component, with patterned conductive features in a lamination structure, and one or more ferrite sheets or other magnetic core structures attached to the lamination structure via one or more inkjet printed magnetic adhesive layers that join the magnetic core structure or structures to the lamination structure.

Additive deposition low temperature curable magnetic interconnecting layer for power components integration

Described examples provide integrated circuits and methods, including forming a conductive seed layer at least partially above a conductive feature of a wafer, forming a conductive structure on at least a portion of the conductive seed layer, performing a printing process that forms a polymer material on a side of the wafer proximate a side of the conductive structure, curing the deposited polymer material, and attaching a solder ball structure to a side of the conductive structure.

Printed repassivation for wafer chip scale packaging

3D-printed protective shell structures for stress sensitive circuits

An integrated circuit ('IC') package comprising an IC die having a top surface and a bottom surface, an elongate member having opposite first and second end portions and a mid portion. The mid portion is positioned proximate the top surface of the IC die. The IC package also includes an encapsulant block having a top surface, a bottom surface and opposite first and second lateral side surfaces. The encapsulant block encapsulates the IC die and the elongate member. Either or both of the first and second end portions of the elongate member are exposed.

Integrated circuit package with sensor and method of making

A method for fabricating packaged semiconductor devices () with an open cavity () in panel format; placing (process) on an adhesive carrier tape a panel-sized grid of metallic pieces having a flat pad () and symmetrically placed vertical pillars (); attaching (process) semiconductor chips () with sensor systems face-down onto the tape; laminating (process) and thinning (process) low CTE insulating material () to fill gaps between chips and grid; turning over (process) assembly to remove tape; plasma-cleaning assembly front side, sputtering and patterning (process) uniform metal layer across assembly and optionally plating (process) metal layer to form rerouting traces and extended contact pads for assembly; laminating (process) insulating stiffener across panel; opening (process) cavities in stiffener to access the sensor system; and singulating (process) packaged devices by cutting metallic pieces.

Open cavity package using chip-embedding technology

In one aspect of the present invention, an integrated circuit package will be described. The integrated circuit package includes at least two integrated circuits that are attached with a substrate. The integrated circuits and the substrates are at least partially encapsulated in a molding material. There is a groove or air gap that extends partially through the molding material and that is arranged to form a thermal barrier between the integrated circuits.

Thermally efficient integrated circuit package

Growing community of inventors

San Jose, CA, United States of America

Luu Thanh Nguyen