Stmicroelectronics (china) Investment Co. Ltd

Luting Ye

Jian Wang

Xiaobo Sun

A resolver decoder circuit includes: a first filter circuit configured to calculate a first weighted sum of a first digital signal over a pre-determined period of time, where the first digital signal includes first digital samples of a first analog signal from a sine winding of a resolver; a second filter circuit configured to calculate a second weighted sum of a second digital signal over the pre-determined period of time, where the second digital signal includes second digital samples of a second analog signal from a cosine winding of the resolver, where the first and the second analog signals are configured to be induced by a sine signal applied to an input winding of the resolver; and a rectifier configured to generate a first output and a second output by adjusting a first sign of the first weighted sum and adjusting a second sign of the second weighted sum, respectively.

Growing community of inventors

Shanghai, China

Luting Ye