Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

TSMC Nanjing Company, Limited

Luping Kong

Ching-Wei Wu

He-Zhou Wan

XiuLi Yang

Kuan Cheng

Ming-Hung Chang

Jun Xie

A memory device is provided and includes a memory array, first to second latch circuits and a gating circuit. Read and write operations are triggered by first and second edges of an internal clock signal respectively. The first latch circuit generates a first output signal in response to an input signal and a first latch clock signal, a first edge of the first latch clock signal generated based on the first edge of the internal clock signal. The second latch circuit generates a second output signal in response to the first output signal and a second latch clock signal, a first edge of the second latch clock signal being between first and second edges of the first latch clock signal. The gating circuit generates, in response to the second output signal and a gating clock generated, a third output signal to the memory array.

Memory structure with optimized latch clock design

A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.

Shared decoder circuit and method

A circuit includes a selection circuit configured to receive a first address from a first port and a second address from a second port, a first latch circuit coupled to the selection circuit and configured to output each of the first address and the second address received from the selection circuit, a decoder, and a control circuit. The control circuit is configured to generate a plurality of signals configured to cause the decoder to decode each of the first address and the second address.

A circuit includes a selection circuit configured to receive a first address at a first input and a second address at a second input, pass the first address to an output when a select signal has a first logical state, and pass the second address to the output when the select signal has a second logical state different from the first logical state. The circuit also includes a decoder configured to decode the passed first address or second address.

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Nanjing, China

Luping Kong