Sony Semiconductor Solutions Corporation

Luonghung Asakura

Chihiro Okada

Yoshiaki Inada

Hiromu Kato

Kengo Iseki

Minoru Sakata

Solid-state imaging elements that accommodate expanded dynamic range are disclosed. In one example, a conversion efficiency control transistor controls conversion efficiency during conversion of a charge into a voltage by opening and closing a path between a floating diffusion layer and an additional capacitance. An upstream amplification transistor amplifies the voltage generated from the charge according to the conversion efficiency, and outputs the voltage to a node. Capacitive elements hold the output voltage. A selecting circuit connects any of the capacitive elements to a downstream node. A downstream circuit reads out and outputs the held voltage via the downstream node.

Solid-state imaging element, imaging device, and solid-state imaging element control method

To improve image quality in a solid-state imaging element that simultaneously performs exposure in all pixels. The solid-state imaging element includes a predetermined number of capacitive elements, a pre-stage circuit, a selection circuit, a post-stage circuit, and a vertical scanning circuit. The pre-stage circuit generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes each of the capacitive elements to hold a corresponding one of the reset level and the signal level. In the selection circuit, a selection transistor that opens and closes a path between one end of each capacitive element and a predetermined node is arranged. The post-stage circuit sequentially reads the reset level and the signal level via the node. The vertical scanning circuit performs control to lower the potential of the one end when the reset level and the signal level are held.

Solid-state imaging element

To improve image quality in a solid-state imaging element that simultaneously performs exposure in all pixels. Arranged in a pre-stage circuit are a pair of floating diffusion layers that converts transferred charges into a voltage, and a conversion efficiency control transistor that controls conversion efficiency with which the charges are converted into voltage by opening and closing a path between the pair of floating diffusion layers. First, second, third, and fourth capacitive elements have their respective one ends commonly connected to the pre-stage circuit. The selection circuit selects one of their respective other ends of the first, second, third, and fourth capacitive elements and connects the selected other end to a predetermined post-stage node. The post-stage circuit reads, via the post-stage node, a reset level obtained by amplifying the voltage when the pair of floating diffusion layers is initialized and a signal level obtained by amplifying the voltage when the charges are transferred.

Solid-state imaging element, imaging device, and method for controlling solid-state imaging element

Image quality enhancement in a solid-state imaging element with simultaneous pixel exposure is disclosed. In one example, a solid-state imaging element includes a first pixel with a first selection transistor that opens and closes a path between a first capacitive element holding a predetermined reset level and a predetermined node, and a second selection transistor that opens and closes a path between a second capacitive element holding a signal level corresponding to an exposure amount and the node. It also includes a second pixel with a third selection transistor that opens and closes a path between a third capacitive element holding a predetermined reset level and a predetermined node, and a fourth selection transistor that opens and closes a path between a fourth capacitive element holding a signal level corresponding to the exposure amount.

Solid-state imaging element and imaging device

PLS resistance is improved in a solid-state imaging element in which all pixels are simultaneously exposed. A front-stage transfer transistor transfers a charge from a photoelectric conversion element to a front-stage charge holding region and a rear-stage charge holding region which have different capacities. A rear-stage transfer transistor transfers the charge from the rear-stage charge holding region to a floating diffusion region. An intermediate transfer transistor transfers a charge, which remains in the front-stage charge holding region after the charge has been transferred from the rear-stage charge holding region to the floating diffusion region, to the floating diffusion region via the front-stage charge holding region.

The present technology relates to a solid-state imaging device and electronic apparatus capable of relieving wiring failure with less redundancy. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is two-dimensionally arranged in a matrix, one redundant wiring provided for n number of signal lines that transmit a pixel signal from the pixels, and one or more redundant switches that connect one signal line and a redundant wiring. The present technology can be applied to, for example, a solid-state imaging device, or the like.

Solid-state imaging device and electronic apparatus

An image capturing device of the present disclosure has a stacked chip structure in which at least two semiconductor chips including a first semiconductor chip and a second semiconductor chip are stacked. Pixels each including a light receiving portion are arranged on the first semiconductor chip, and a scanning section that selectively scans the pixel and a signal processing section that processes an analog signal output from the pixel are arranged on the second semiconductor chip. Further, the scanning section is arranged along pixel rows of the pixel arrangement in the matrix form.

Image capturing device and electronic apparatus with stacked chip structure

An imaging device that includes a plurality of pixels each including a photoelectric conversion element and arranged in an array of matrix, a control line group including a plurality of control lines for controlling each of pixels aligned in a row direction, each arranged in each of rows of the array, and a plurality of reading lines (VSL) arranged in each of columns for transferring a pixel signal read from each of pixels aligned in a column direction of the array, wherein the plurality of pixels includes a first pixel controlled by a control signal supplied from a first control line group including control lines in a first number among a plurality of control lines included in the control line group in each of pixels aligned in the row direction in at least one of rows of the array.

Imaging device and electronic device

In one example, an imaging device includes stacked first and second substrates. The first substrate has an array of light receiving pixels divisible into pixel blocks and the second substrate has a pixel control portion that controls the pixels. The first substrate includes a first wiring line that transmits a first voltage, a second wiring line that transmits a second voltage, and a fault detection circuit that detects a wiring fault for each pixel block. The fault detection circuit detects a wiring fault by connecting wiring lines corresponding to pixel columns or pixel rows in series in each pixel block, connecting one of the ends of a wiring chain connected in series in each pixel block to the first wiring line, connecting the other end to the second wiring line, and detecting a wiring fault based on a potential at an intermediate position of the wiring chain.

Imaging device and electronic equipment

Solid-state imaging elements are disclosed. In one example, an upstream circuit sequentially generates a predetermined reset level and a signal level corresponding to an exposure amount, and causes first and second capacitive elements to hold the reset level and the signal level. A selection circuit sequentially connects one of the capacitive elements to a predetermined downstream node, disconnects both capacitive elements from the downstream node, and connects the other capacitive element to the downstream node. A downstream reset transistor initializes a level of the downstream node when both capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the signal level from the first and second capacitive elements via the downstream node and outputs the reset level and the signal level.

A first and second pixel units that perform FD addition are provided. The first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to an FD; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node. The second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to an FD; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node. The respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other.

Imaging apparatus and electronic device

Solid-state imaging elements are disclosed. In one example, an upstream circuit block generates a predetermined reset level and a plurality of signal levels each corresponding to an exposure amount, and causes capacitive elements, different from each other, to hold them. A selection circuit sequentially performs control to connect the capacitive element in which the reset level is held to a predetermined downstream node, control to disconnect capacitive elements from the downstream node, and control to connect the capacitive element in which any of the plurality of signal levels is held to the downstream node. A downstream reset transistor initializes a level of the downstream node when the capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the plurality of signal levels via the downstream node.

Solid-state imaging apparatuses are disclosed. In one example, an apparatus includes a first substrate and a second substrate. The first substrate includes a pixel array that is arrayed in columns and rows. The second substrate is stacked on the first substrate, and includes first and second analog circuits that overlap with the pixel array in a third direction intersecting the column and row directions. A pixel divider section divides pixels in the array into a first area and a second area. The first and second analog circuits respectively connect to pixels in the first and second areas, and are adjacent to each other with a circuit divider section interposed therebetween, the circuit divider section being located with an overlap with the pixel divider section in the third direction.

Solid-state imaging apparatus

In a pixel array unit, pixels that generate pixel signals are arranged in a matrix. A control unitperforms reading of pixel signals in a first mode in which reading of the pixel signals is performed by thinning out lines from the pixel array unit, and reading of pixel signals in a second mode in which reading of the pixel signals is performed by including the lines thinned out in the first mode after the reading in the first mode. A signal processing unituses a pixel signal read in the first mode and a pixel signal read in the second mode, to set an amount of correction for a pixel of the lines thinned out in the first mode, on the basis of the pixel signal read in the second mode from a pixel in which reading of the pixel signal is performed in the first mode and the second mode, and corrects the pixel signal read in the second mode from the pixel of the lines thinned out in the first mode with the set amount of correction to reduce an influence of leakage light.

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Kanagawa, Japan

Luonghung Asakura