Cadence Design Systems, Inc.

Lung-Chun Liu

Wei-Jin Dai

Ping-Chih Wu

Thad Clay McCracken

Disclosed are improved approaches for implementing design entry. An efficient, spread-sheet based representation is provided for both the instances and connections in a design. Visualization techniques provide the user with visual cues, to direct and identify compatible connection points, unconnected instances, and contention situations. Techniques are disclosed to automatically filter the spreadsheet in a variety of ways, to help the user to dynamically hide portions of the design space that are not interesting at a particular time, and thus to improve the efficiency with which they can work.

Method and system for implementing electronic design entry

A method for displaying a schematic diagram of a circuit showing multiple time-frame signal values across storage elements includes identifying one or more time-frames in a circuit. The one or more time-frames are determined from a number of consecutive storage elements in a signal path in the circuit. The method also includes receiving a request to display signal values associated with a first storage element at a time-frame t. The method further includes displaying a first signal value carried on a first signal line coupled to an output of the first storage element at time-frame t and displaying a second signal value carried on a second signal line coupled to an input of the first storage element at time-frame t&minus;1. In another embodiment, the method identifies any loops that are in the circuit. In a loop, a signal value comes from a gate at a time-frame and loops back to a loop-back gate at an earlier time-frame. Having identified a loop in the circuit, the method displays elements in the loop at different time-frames instead of showing the loop in the schematic representation.

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Saratoga, CA, United States of America

Lung-Chun Liu