Ememory Technology Inc.

Lun-Chun Chen

Hsin-Ming Chen

Ping-Lung Ho

Meng-Yi Wu

Chun-Hung Lin

Tung-Cheng Kuo

Chih-Hao Huang

Chin-Yi Chen

Yueh-Chia Wen

Jiun-Ren Chen

An antifuse-type one time programming memory cell at least includes an antifuse transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. The first nanowire is surrounded by the first gate structure. The first gate structure comprises a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Antifuse-type one time programming memory cell with gate-all-around transistor

An antifuse-type one time programming memory includes a first memory cell. The first memory cell includes at least one antifuse transistor. The antifuse transistor is forksheet transistor. The antifuse transistor includes a first nanowire, a first gate structure, a first drain/source structure and a second drain/source structure. A first-portion surface of the first nanowire is contacted with the isolation wall. A second-portion surface of the first nanowire is contacted with the first gate structure. The first gate structure includes a first spacer, a second spacer, a first gate dielectric layer and a first gate layer. The first drain/source structure is electrically contacted with a first terminal of the first nanowire. The second drain/source structure is electrically contacted with a second terminal of the first nanowire.

Antifuse-type one time programming memory with forksheet transistors

An OTP memory cell includes an antifuse transistor, a first transistor and a second transistor. The antifuse transistor includes a first fin, a second fin, a first gate structure, a first drain/source contact layer and a second drain/source contact layer. A central region of the first fin and a central region of the second fin are covered by a first gate structure. The first drain/source contact layer is electrically connected with a first terminal of the first fin and a first terminal of the second fin. The second drain/source contact layer is electrically connected with a second terminal of the second fin but not electrically connected with a second terminal of the first fin. The first transistor is connected with the first drain/source contact layer. The second transistor is connected with the second drain/source contact layer.

One time programming memory cell with fin field-effect transistor using physically unclonable function technology

An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

Antifuse-type one time programming memory cell and cell array structure with same

A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

Semiconductor apparatus with fake functionality

Provided is an OTP memory cell including a first antifuse unit, a second antifuse unit, a select transistor, and a well region. The first and the second antifuse unit respectively include an antifuse layer and an antifuse gate disposed on a substrate in sequence. The select transistor includes a select gate, a gate dielectric layer, a first doped region, and a second doped region. The select gate is disposed on the substrate. The gate dielectric layer is disposed between the select gate and the substrate. The first and the second doped region are respectively disposed in the substrate at two sides of the select gate, wherein the second doped region is disposed in the substrate at the periphery of the first and the second antifuse unit. The well region is disposed in the substrate below the first and the second antifuse unit and is connected to the second doped region.

Growing community of inventors

Yilan County, Taiwan

Lun-Chun Chen