Continental Teves, Ag and Company Ohg

Freescale Semiconductor,inc.

Lukusa Didier Kabulepa

Adrian Traskov

Houman Amjadi

Thorsten Ehrenberg

Wolfgang Fey

Anthony M Reipold

Andreas Kirschbaum

Daniel Baumeister

Felix Wolf

Anthony Reipold

A redundant two-processor controller having a first processor () and a second processor () for the synchronous execution of a control program. The controller having at least a first multiplexer () for optionally connecting at least a first peripheral unit () to be actuated to one of the two processors (), and at least a first Comparison unit () for monitoring the synchronization state of the two processors () and for detecting a synchronization error. A restoration control unit () is designed to monitor the execution of at least one test program by the two processors () after the occurrence of a synchronization error and to evaluate the test results, and which is designed to configure at least the first multiplexer ().

Redundant two-processor controller and control method

A control computer system comprising at least two modules () which are designed to be redundant with respect to one another. The control computer system having at least one comparison unit () for monitoring the synchronization state of the at least two redundant modules () and for detecting a synchronization error at least one peripheral unit (). At least one switching matrix () which is set up to allow or block access to the at least two redundant modules or access to the peripheral unit () by the at least two redundant modules, and an error-handling unit () which is set up to receive signals from the at least one comparison unit () and to drive the at least one switching matrix () in order to completely or selectively prevent access to the at least two redundant modules or access to the peripheral unit by the at least two redundant modules.

Control computer system, method for controlling a control computer system, and use of a control computer system

A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.

Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product

A checking method in which serial data protected by check data are transmitted via a serial data bus from a transmitter to a receiver, the receiver then conditions the data and compares them with the transmitted check data in order to recognize transmission errors, wherein the transmitter bases the production of the check data and the receiver bases the conditioning of the data on the same check data formation method, wherein the check data formation/conditioning is performed using error recognition hardware, wherein the region of the receiver contains not only the error recognition hardware but also error recognition software which are used to additionally check the received data, and wherein also an error in the transmitted data and/or check data is caused by a transmitter-end error stimulation. A transmission and reception circuit for carrying out the above method and also the use thereof is also disclosed.

Checking method and electronic circuit for the secure serial transmission of data

A semiconductor memory and a data processing system having hardware for carrying out a method for the improved internal monitoring of addressing circuits in semiconductor memories or in a data processing system, in which logic levels addressing lines are tapped off, the actually selected address or subaddress is represented by additional address bit lines, the actually accessed address/subaddress is recovered using the address bit lines, and the actually selected address/subaddress is compared with the applied address/subaddress, obtained from the additional address bit lines, in order to recognize an error in the addressing circuit.

Growing community of inventors

Erzhausen, Germany

Lukusa Didier Kabulepa