Nvidia Corporation

Luke Y Chang

Steven E Molnar

Emmett Michael Kilgariff

Michael J M Toksvig

Alexander Lev Minkin

Karim Abdalla

David Kirk McAllister

Joel James McCormack

Gary C King

Paul S Heckbert

John W Berendsen

Bo Hong

Walter E Donovan

Narayan Kulshrestha

Don Templeton

Walter Donavan

A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.

Package level power gating

Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Reconfigurable high-performance texture pipeline with advanced filtering

Reconfigurable high performance texture pipeline with advanced filtering

Circuits, methods, and apparatus that reduce the amount of data transferred between a graphics processor integrated circuit and graphics memory. Various embodiments of the present invention further improve the efficiency of blenders that are included on a graphics processor. One embodiment provides for the storage of a reduced number of subsamples of a pixel when the storage of a larger number of subsamples would be redundant. The number of subsamples that are blended with source data are compressed, thereby reducing the task load on the blenders increasing their efficiency. These methods can be disabled to avoid errors that may arise in certain applications.

Optimized alpha blend for anti-aliased render

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San Mateo, CA, United States of America

Luke Y Chang