Via Technologies, Inc.

Via Optical Solution, Inc.

Luke Wen

William Mar

Yuan-Kun Hsiao

Pei-Chieh Hu

A data phase locked loop circuit includes a phase locked loop circuit, a judging circuit, a detecting circuit and a control circuit. The phase locked loop circuit outputs a reference signal according to a data signal, which is generated by an optical drive reading an optical disk. When the judging circuit judges that a jitter signal is smaller than a threshold value, the control circuit stores a frequency of the reference signal. When the detecting circuit detects a defect zone of the optical disk read by the optical drive, the phase locked loop circuit fixes the frequency of the reference signal to a latest stored one.

Data phase locked loop circuit and method for generating frequency of reference signal thereof

An apparatus for generating a wobble clock includes an operation circuit for receiving a wobble signal and counting cycles of an oscillating signal during a cycle of the wobble signal to derive a cycle value and for comparing the cycle value with a preset cycle value to output a first protection signal, and a phase-locked loop circuit connected to the operation circuit for receiving the wobble signal, the wobble clock and the first protection signal, and determining whether the wobble clock is to be synchronized with the wobble signal according to the first protection signal.

Method and related apparatus for decoding information carried by wobble signals

A method and related apparatus for providing a clock synchronized with an input signal. The method includes generating an estimated rate according to transitions in the input signal, processing a dithering step for updating the estimated rate by multiplying it with a predetermined ratio, and adjusting the frequency of the clock according to the updated estimated rate. The predetermined ratios used in repeated dithering steps are modified according to a predetermined rule such that the predetermined ratio is different when the dithering steps are repeated.

Method and related apparatus for locking phase with estimated rate modified by rate dithering

A method for recovering a data required to have n consecutive and repetitive bits is disclosed. The data is obtained by converting a sample value sequence into a binary sequence according to a preset value and the data having n&minus;1 consecutive first-level bits and two second-level bits immediately adjacent to two end bits of the n&minus;1 consecutive first-level bits, respectively. The method corrects one of the two second-level bits, which has a corresponding sample value closer to the preset value than the other, into another first-level bit to obtain n consecutive first-level bits. In addition, a device for recovering a data to be decoded is also disclosed.

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Taipei Hsien, Taiwan

Luke Wen