International Business Machines Corporation

Luke M Hopkins

Raymond Michael Higgs

Mushfiq U Saleheen

Gabriel Martel Tarr

Clinton E Bubb

Howard M Haynie

Michael Grassi

Kirk D Pospesel

Christopher J Colonna

Richard Mark Sczepczenski

George Kuch

Mahmoud Amin

Ying-Yeung Li

Dan Vangor

Daniel Hughes

Myron Wisniewski

Pascal R Bastien

Margaret Frances Kaelin Dubowsky

Anmar A Al Zubaydi

Pasquale A Catalano

Michael James Becht

Stephen Robert Guendert

Theodore R Maeurer

Steven George Aden

Anthony Grech

Aspects include obtaining data to be transformed. A selected transformation to be applied to the data is determined based on a storage block address list entry (SBALE) in a storage block address list (SBAL). The SBALE includes at least one field that is used in determining the selected transformation to be applied. The selected transformation is applied on the data to generate transformed data and the transformed data is placed in a location specified by the SBAL.

Storage block address list entry transform architecture

Aspects of the invention include receiving an error code describing a computer hardware or firmware error. A list of data items to be collected to assist in correcting the error is received. The contents of the list are selected based at least in part on the error code and are in priority order. The data items in the list are collected and a buffer to store the collected data items is selected. At least a subset of the collected data items to be written is transmitted to the buffer. All of the collected data items are transmitted to the buffer when the buffer is large enough to hold all of the data items in the list. A subset of the collected data items are transmitted to the buffer in priority order when the buffer is not large enough to hold all of the data in the list.

Dynamic logging and prioritization of error incident data

According to one or more embodiments of the present invention, a computer-implemented method includes receiving a request to update a layout of a user interface being rendered. The method further includes receiving a user input for an element of the user interface. The method further includes determining whether the user input is received within a predetermined duration since receiving the request to update the layout. The method further includes, based on a determination that the user input is received after completion of the predetermined duration, accepting the user input. The method further includes, based on a determination that the user input is received prior to completion of the predetermined duration, rejecting the user input.

Avoiding bad input during user interface layout changes using snapshots

Aspects of the invention include receiving an error code describing a computer hardware or firmware error. A list of data items to be collected to assist in correcting the error is built. The contents of the list are selected based at least in part on the error code and are in priority order. The data items in the list are collected and a buffer to store the collected data items is selected. At least a subset of the collected data items to be written is transmitted to the buffer. All of the collected data items are transmitted to the buffer when the buffer is large enough to hold all of the data items in the list. A subset of the collected data items are transmitted to the buffer in priority order when the buffer is not large enough to hold all of the data in the list.

Technical solutions are described for executing a computer instruction including an asynchronous operation. An example method includes computing parameters associated with the asynchronous operation, and transmitting a command for executing the asynchronous operation by an external device. The method also includes intercepting and storing, by an interface logic controller, the parameters associated with the asynchronous operation into one or more log registers. The method also includes receiving a response to the asynchronous operation. In response to the asynchronous operation being a success, executing a next instruction by the processing element. In response to the asynchronous operation being a failure, a processing element accesses the parameters from the log registers, and restarts the asynchronous operation using the parameters from the one or more log registers.

Executing computer instruction including asynchronous operation

Technical solutions are described for a supervisory processor to pass an out-of-band communication to a target processor in a multiprocessor system. For example, a first processor in a multi-processor system includes a register configured to store a command from a second processor of the multi-processor system, and to store a response to the command from the second processor. The first processor determines that the second processor has issued the command for execution by the first processor based on a first portion of the register being set to a first state, which is a predetermined state. The first processor also, responsively, reads the command from the second processor by parsing a second portion of the register. The first processor includes executes the command and stores the response for the command in the register.

Remote command invocation using a register for storing a command and an attention bit indicating command has been issued

Embodiments are directed to a method of optimizing power consumption in an electrical device. The method includes receiving, by a processor, instructions to enter a wait state, and identifying, by the processor, a parameter associated with the instructions to enter a wait state. The method continues with initiating, by the processor, instructions to enter a low-power mode based on the parameter, initiating, by the processor, instructions to exit a low-power mode based on the parameter, and providing, via a user interface, a user with notice of a current state of the processor. The parameter includes runtime information, instructional information, and scheduled operations.

Processor power-saving during wait events

A system for managing one or more queues in a multi-processor environment includes a shared memory configured to be accessed by a plurality of processing elements, and a queue manager configured to control a queue in the shared memory, the queue manager storing dynamically configurable queue parameters including an operation address associated with the queue, a number of queue elements and a size of each queue element. The queue manager is configured to intercept a message from a processing element, the message directed to the shared memory and specifying the operation address, calculate an address of a location in the shared memory corresponding to one or more available queue elements, the calculating performed based on the operation address, the number of queue elements, and the size of each queue element, and perform one or more queuing operations on the queue based on the calculated address.

Configurable hardware queue management and address translation

A system for managing one or more queues in a multi-processor environment includes a queue manager disposed in communication with a plurality of processors and a memory shared by the plurality of processors, and a queue configured to be controlled by the queue manager, the queue including independent and discrete queue elements and having a starting location specified by a base address, the queue manager having one or more dynamically configurable parameters, the one or more dynamically configurable parameters including a size of each of the queue elements. The queue manager is configured to perform receiving a message from a processor of the plurality of processors, the message including an operation address specifying a fixed storage location in the memory and a request related to accessing the memory, selecting the queue based on the operation address, and performing a queuing operation on the queue based on the request.

Configurable hardware queue management

Technical solutions are described for profiling an execution of a computer program. An example method includes setting a program-counter indicator to a first state in response to updating a program counter register. The method further includes profiling the execution of the computer program by periodically sampling the program counter register according to a sampling time-interval. Sampling the program counter register includes recording a content of the program counter register in response to the program-counter indicator being in the first state. The method also includes increasing the sampling time-interval.

Lightweight profiling using branch history

An exemplary embodiment of the present invention is a method and system for isolating dropped packets in a computer network. A request for network analysis that includes a source node and a destination node is received by the invention. A map of the expected path between the two points, including the probes along the route is then generated. A capture filter profile for each probe along the route is created. A request to perform data collection is transmitted, along with the capture filter profile, to each of the probes along the route. Data is received back from the data collection in the form of a data log. Exception data is generated by comparing the data log to the expected path between the two points. Additional embodiments include a system and storage medium for isolating dropped packets in a computer network.

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Poughkeepsie, NY, United States of America

Luke M Hopkins