Intel Corporation

Other

Luke L Chang

Ilango S Ganga

Andrey Vladimirovich Belogolovy

Andrei Ovchinnikov

Jayakrishna Guddeti

Naichih Chang

Pak-Lung Seto

James R Vash

Bradley John Booth

Junaid Thaliyil

Rajesh M Sankaran

Mahesh S Natu

Robert J Safranek

Herbert H Hum

Victor Lau

Gregory Cummings

Ganesh Kumar

Manoj K Arora

David Bubien

Eric Gouldey

Chandra P Joshi

Michelle M Sebot

Pak-Iung Seto

Noam Avni

Benzi Ende

Simcha Pearl

Mahak Gupta

Gershon Bar-on

Ovchinnikov Andrei

Sorana Lazarovici

Lavanya Nama

Junaid F Thaliyil

The door breaching system is capable of removing or opening a door attached to a structure. A main tether made up of a tether strap and multiple eyelets attaches to a vehicle through one of the eyelets at one end of the tether strap. The other end of the tether strap attaches to at least one hook strap through a master link. Each hook strap has a hook at a distal end. In use, at least one sling loops through part of the door. Sling eyelets on either end of a sling strap connect to the hook. Due to the secure connection between the door and the door breaching system, moving the vehicle away from the structure removes the door in a controllable fashion.

Door breaching system and method

An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

Posted interrupt architecture

Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to generate a forward error correction (FEC) block comprising a shortened cyclic code comprising 32 rows of a particular number of bits, the particular number of bits comprise payload bits generated from output of the PCS and one or more bits of transcoding overhead, wherein the FEC block further comprises 32 parity bits at the end of the FEC block. The FEC block is scrambled using a pseudo-noise sequence. The FEC block is sent to a physical medium attachment (PMA) sublayer of the physical layer.

Techniques to perform forward error correction for an electrical backplane

In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at least one function; a root complex including a first root port to interface to a first device to be coupled to the apparatus via a first interconnect and a second root port to interface to the agent via a bridge logic; and the bridge logic to interface the second root port to the agent, convert a first transaction from the first root port having a first format to a second format and communicate the first transaction having the second format to the agent. Other embodiments are described and claimed.

Method, apparatus and system for integrating devices in a root complex

A media independent interface and circuitry of a forward error correction (FEC) sublayer are provided, the circuitry of the FEC sublayer to perform forward error correction, the FEC sublayer coupled to a physical coding sublayer and a physical medium attachment (PMA) sublayer. The FEC sublayer include an encoder having a reverse gearbox, a compressor coupled to said reverse gearbox, a selector coupled to said compressor, a parity generator coupled to said compressor, a multiplexer coupled to said compressor, selector and said parity generator, a scrambler coupled to said multiplexer, and a pseudo-noise generator coupled to said scrambler.

Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests.

Dual casting PCIE inbound writes to memory and peer devices

Responsive to receiving a write request for a cache line from an input/output device, a caching agent of a first processor determines that the cache line is managed by a home agent of a second processor. The caching agent sends an ownership request for the cache line to the second processor. A home agent of the second processor receives the ownership request, generates an entry in a directory cache for the cache line, the entry identifying the remote caching agent as having ownership of the cache line, and grants ownership of the cache line to the remote caching agent. Responsive to receiving the grant of ownership for the cache line from the home agent an input/output controller of the first processor adds an entry for the cache line to an input/output write cache, the entry comprising a first indicator that the cache line is managed by the home agent of the second processor.

Directory cache supporting non-atomic input/output operations

Techniques to perform forward error correction for an electrical backplane are described including forward error correction (FEC) circuitry to perform forward error correction, physical coding sublayer circuitry, and physical medium attachment (PMA) circuitry. The FEC circuitry provides primitives comprising a FEC_UNITDATA.request primitive, a FEC_UNITDATA.signal primitive, and FEC_UNITDATA.indication primitive, the FEC sublayer and includes an encoder having a reverse gearbox and a pseudo-noise generator.

Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity.

Tunneling platform management messages through inter-processor interconnects

Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.

Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error correction sublayer to perform forward error correction using a single bit to represent a two bit synchronization header.

In some embodiments, a shared IO device includes a plurality of packet filters associated with a plurality of virtual systems sharing the shared I/O device and a plurality of filter receive queues assigned to the plurality of packet filters. A processor is responsive to a receive packet to determine if the receive packet matches one of the plurality of packet filters and the processor, upon determining that there is a matched packet filter, is adapted to place the receive packet in the filter receive queue assigned to the matched packet filter.

Shared input-output device

In one aspect, a shared transport layer frame information structure (FIS) generation logic may generate FISes for each of a plurality of SATA ports. In a further aspect, a port addressing logic, in communication with the shared transport layer FIS generation logic, may select one of the SATA ports for each of the FISes.

Serial ATA port addressing

Disclosed are a system, method and device for negotiating a data transmission mode over an attachment unit interface (DDI). A data transceiver circuit may be coupled to one or more data lanes of the DDI. A negotiation section may receive a link pulse signal on at least one data lane in the DDI during a negotiation period and selectively configure the data transceiver to transmit and receive data on one or more data lanes according to a data transmission mode based upon the received link pulse signal.

Growing community of inventors

Marlboro, MA, United States of America

Luke L Chang