Intel Corporation

Luke E Girard

Harshvardhan P Sharangpani

Francis X Mckeen

James A Sutton, Ii

David T Hass

Kelan Craig Silvester

Michael Francis O'Connor

Michael Paul Corwin

Sundeep M Bajikar

Daniel J Lenehan

Jonathan B Sweedler

Ken Arora

Ron Zinger

Syed Reza

Steven G Preston

Jeff Schiffer

Anne Gregory

In one embodiment, the invention provides a method comprising storing user authentication information in a hardware structure of a computer system, the hardware structure including a security mechanism to protect the stored authentication information from unauthorized access, and authenticating a user of the computer system by comparing user input authentication information with the stored authentication information.

Method and system and authenticating a user of a computer system that has a trusted platform module (TPM)

A method for deterring unauthorized use of an electronic device is described. The method includes installing security data in a protected storage area, installing a security routine operable to check for the security data, and prompting a user for identity information if the security data is found, before permitting use of the device. In an implementation, the device is shut down if the identity information is incorrect, and manufacturer contact information may be displayed before shutting down. But if the user responds correctly, the activation process is continued to enable normal operation of the device.

Deterring unauthorized use of electronic devices

According to one embodiment, a network is disclosed. The network includes a server computer and a client computer. The client computer accesses an authentication stack during power on self test (POST) that enables authentication of boot code that is to be downloaded from the server computer prior to control being passed to the operating system.

Mechanism to improve authentication for remote management of a computer system

According to one embodiment a method is disclosed. The method includes receiving encrypted video data at a graphics controller from a microprocessor, decrypting the data at the graphics controller and rendering the data.

Method and apparatus to improve the protection of information presented by a computer

A wireless network transmits digital data. The network includes an active transceiver to transmit carrier waves at a succession of preselected frequencies and a transponder. The transponder transmits digital data to the active transceiver by partially reflecting the carrier waves.

Wireless digital data transmission from a passive transceiver

An improvement to a graphics controller to prevent the contents of selected portions of the frame buffer from being read by devices external to the graphics controller. The invention defines one or more viewable rectangles in the frame buffer as a protected write-only area. Any attempt to read data from the protected area of the frame buffer triggers a security violation which can delete or destroy the contents of that area to prevent it from being read. The controller can also operate in a bypass mode in which the security functions are bypassed so the graphics controller operates in a conventional manner. A security violation may return the controller to the bypass mode. The invention can prevent protected data, such as copyrighted data downloaded over the Internet, from being copied from the frame buffer and used in an unauthorized manner.

For one embodiment of the present invention, a protected storage device of a computer system includes a password stored therein. Instructions may be included on the computer system to authenticate the user. Once authenticated, the password may be transferred to a hard drive where it may be used to unlock the drive. Subsequent to unlocking the drive, an operating system may be loaded. For one embodiment of the present invention, the drive may be relocked by reducing the voltage supplied to the drive in accordance with a power management policy. The drive may be again unlocked by re-authenticating the user and transferring the password from protected storage to the drive.

Method and apparatus for unlocking a computer system hard drive

A system and method for protected messaging. The method comprises providing a first interface to a protected storage medium to enable a pre-operating system software program access to the protected storage medium. Similarly the method also comprises providing a second interface to the protected storage medium to enable an operating system present software program access to the protected storage medium. In one embodiment, the method comprises enabling a pre-operating system software program to pass information to and receive information from an operating system present software program or another pre-operating system software program by accessing a protected storage medium via the first interface. In another embodiment, the method comprises enabling an operating system present software program to pass information to and receive information from a pre-operating system software program or another operating system present software program by accessing the protected storage medium via the second interface. The method may be implemented on any personal computing device.

System and method for protected messaging

A method and apparatus for authenticating a user's identity are disclosed. In one embodiment, a data collector continuously receives and collects a stream of biometric data from a user. After the data collector passes on the biometric data to a data matcher, the data matcher continuously processes the data to authenticate the user's identity.

Continuous verification system

The present invention relates to wirelessly locking a computer platform to discourage theft as the platform is transported in a distribution channel. A computer platform having a chipset, a random access memory (RAM) coupled to the chipset, a central processing unit coupled to the chipset, a protected storage device in communication with the chipset, and a wireless communication device coupled to the chipset is presented. A radio signal having an authentication lock is introduced into the wireless communication device. The authentication lock is then placed in the protected storage device. The computer platform is placed in the distribution channel.

Protection of laptop computers from theft in the stream of commerce

A pipelined data processor has instructions at different stages of execution. Some of the instructions specify virtual addresses into a file of registers having physical addresses. A speculative translator maps the virtual registers of an instruction at one pipeline stage into physical registers for speculative use by the instruction at a later pipeline stage. The registers have multiple differently translated regions. Failure of speculative renaming reverts to an archive copy of renaming data.

Speculative renaming of data-processor registers

A hardware implementation for quotient prediction overrule in high speed higher radix SRT division computation circuits. A quotient prediction PLA receives a data segment of the divisor, together with data values from one or more multiplexors. One multiplexor receives as input a partial remainder from a carry-propagate-adder (CPA), which CPA combines into nonredundant form redundant sum and carry vectors derived from a carry-save-adder (CSA) which determines the next partial remainder. The PLA evaluates the next most significant bits (MSBs) of the divisor together with the next MSBs of the next (unlatched) partial remainder to determine the next quotient bits. The quotient estimates given by the quotient prediction PLA are then transmitted to both quotient and remainder generation logic, including a divisior multiple gating multiplexor. The quotient estimate signals together with a sign signal determine the divisor multiple to be used in the next division iteration during the next clock cycle. When ordinary quotient prediction is to be overridden, the state machine sends an appropriate control signal one clock cycle early, whereafter a divisor multiple of zero is combined with the current partial remainder. A divisor multiple of zero causes a previously derived remainder to be recycled unchanged in the remainder datapath, thereby permitting multicomponent data values (i.e., quotient and remainder) to be sequentially routed along a shared datapath and single output bus. Other non zero divisor multiples can be used to force particular mathematical operations at chosen times. By determining the next quotient bits and the divisor multiple in the current clock cycle the divisor multiple before the the speedpath of the SRT division implementation is substantially improved.

Method and apparatus for overriding quotient prediction in floating

A hardware floating point remainder generator is disclosed for performing a remainder (REM) function by receiving two floating point numbers (X and Y), by generating the remainder of X/Y according to a series of radix 4 SRT non-restoring division cycles and at most one single bit restoring division step, and by delivering the remainder.

Floating point remainder generator for a math processor

A hardware logic arrangement for subtraction using a 3:2 carry-save-adder (CSA) for use with high speed floating point computation circuits. Three operands to be combined are routed to the three inputs of the CSA via separate multiplexors (MUXs) and appropriate inverting logic. Output sum and carry vectors are routed via further MUXs to separate latch storage registers. Subtraction executed as addition of the inverse of an operand is implemented by routing a constant '1' to the MUX steering the output carry vector to its associated latch.

Methods and apparatus for subtraction with 3:2 carry-save adders

A hardware logic arrangement for quotient correction in high speed higher radix non-restoring division computation circuits producing alternative quotient results of the form Q and Q-1. A two bit per clock quotient bit stream is taken as the output from an divider and selectively latched into positive and negative weighted quotients. These redundant vectors are then seperately steered via appropriate steering logic to a carry-propogate-adder (CPA). An exclusive-OR (XOR) logic block is inserted between the steering logic for one of the vectors and the subtrahend input of the CPA. Operation of the XOR block is governed by a first control signal. A second control signal is coupled to the carry-in input of the CPA. After the last iteration of the division sequence, either Q or Q-1 alternative forms of the result quotient may be produced in the clock cycle required by selectively invoking 2's complement addition when combining the redundant weighted quotients. Where the quotient Q is required, asserting the first control signal to the XOR block inverts the datavalue transmitted to the subtrahend input of the CPA, whereafter both addend and subtrahend inputs are added together in the presence of the second control signal asserted to the carry-in input of the CPA, adding 1 to the sum. Where the alternative result Q-1 is required, only the first control signal is asserted to the XOR block to invert the datavalue transmitted to the subtrahend input of the CPA, whereafter the addend and subtrahend inputs are simply added together.

Growing community of inventors

Santa Clara, CA, United States of America

Luke E Girard