International Business Machines Corporation

Luke C Lang

Martin Aureliano Hassner

Norman Ken Ouchi

Paul Wingshing Chung

Ralph L Gee

Uwe Schwiegelshohn

Paik Saber

The error correction code capability of the linear recording density of a zone of contiguous recording tracks on a surface or volume having at lest two zones of different average linear recording density is adjusted. Each zone has associated therewith a parameter pair (r,R) defining the number of error correction bytes r to be appended to data blocks to form a codeword written to tracks within the zone and the number R.ltoreq.(r/2-1) of correctable errors in the event of a non-zero remainder detected upon readback of a codeword from a track within the zone. The r parameter controls the length of a shift register type encoder syndrome generator.

Location dependent variable error correction processing for multi-track

A method and means for setting the free-running frequency of a voltage controlled oscillator (VCO) without requiring laser trimming or the like is described. The VCO forms part of an interconnected phase-locked loop (PLL) and frequency-locked loop (FLL). At system power on, the PLL is automatically disabled and a digital-to-analog (DAC) in the PLL is set to a value corresponding substantially to the center of a preselected lock range. The FLL, which includes a second DAC, then operates to generate a bias voltage for incrementing or decrementing the VCO output frequency until the VCO pulse count stored in a register equals an expected count; whereupon the VCO will be set at its free-running frequency. When the PLL is enabled, a phase error generator generates a digital phase error signal from the input data. A digital integrator converts the phase error signal to a digital frequency error signal. These error signals are added and the result is supplied to the DAC in the PLL for providing an analog output indicative of PLL frequency error. The outputs from both DACs are summed and the resultant current is converted to a bias voltage to adjust the VCO frequency as necessary for normally maintaining it within said lock range. If the VCO frequency deviates from said range, the frequency error signal to the PLL DAC is zeroed, and the frequency error signal is supplied to the FLL DAC. The phase error signal from the PLL DAC and the signal from the FLL DAC as modified by the frequency error signal are summed, and the resultant current in converted to a bias voltage to adjust the VCO frequency to within said lock range.

Setting and dynamically adjusting VCO free-running frequency at system

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Santa Clara, CA, United States of America

Luke C Lang