Intel Corporation

Luke A Johnson

Adhiveeraraghavan Srikanth

Wenjun Yun

Timothy E Fiscus

Michael A Brown

Yueming He

John K Schwartzlow

Bruce Querbach

Mark A Beiley

Ronald W Swartz

Waleed Khalil

John Maddux

Bobby B Nikjou

Chia How Low

Rizwan Ahmed

Sleiman Bou-Sleiman

Mun Fook Leong

Mahesh J Deshmane

Rajashri Doddamani

Budiyanto Junus

Sleiman Bou Sleiman

James Tseng

Donald Rush

Meetul Goyal

Randall B Hamilton

Minyoung Kim

Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to electronically couple with the reference device such that only one circuit unit of the plurality of circuit units is electronically coupled to the reference device at a given time while other circuit units of the plurality are electronically uncoupled to the reference device during that time.

Apparatus for providing shared reference device wherein an internal device is calibrated using reference device via calibrated circuit

Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Low power equalizer and its training

Apparatus for providing shared reference device with metal line formed from metal layer with lower resistivity compared to other metal layers in processor

Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a reference generator to generate an adjustable compensated reference signal; a bias generator to generate a bias signal based on the adjustable compensated reference signal; a transmitter coupled with the bias generator to transmit an output signal; and a feedback mechanism to sample the output signal from the transmitter and to provide the sampled output signal to the bias generator.

Method and apparatus for minimizing within-die variations in performance parameters of a processor

Various embodiments include apparatus, systems, and methods having a reference node to receive a reference voltage, a first node to provide a signal, and a circuit. Such a circuit may include a second node to receive different voltages greater than the reference voltage and to cause the signal at the first node to switch between a first voltage greater than the reference voltage and a second voltage greater than the reference voltage. Other embodiments including additional apparatus, systems, and methods are described.

Apparatus, system, and method for voltage level switching

Methods and systems to calibrate an on-die resistor relative to an operating voltage of an on-die push-pull driver, and to calibrate the push-pull driver relative to the on-die resistor and relative to operating voltages of the push-pull driver. The calibrated on-die resistor may be used to calibrate receive terminations, a differential transmit termination, and a simulated far-end differential receive termination. The calibrated differential transmit termination and simulated far-end differential receive termination may be coupled in parallel to calibrate current drivers. Calibration of the current drivers may include calibrating voltage swing, and may include a first phase that simultaneously adjusts compensation to the current drivers, and a second phase that individually adjusts the compensation to the current drivers.

Methods and systems to calibrate push-pull drivers

A method and an apparatus for detecting a number of variation in resistance within a material stack in response to a scanning and injection of a non-contacting electron stream into a material stack, the material stack having a first conductive contact layer, a variable resistive layer, a fixed resistive layer, and a second conductive contact layer, and the variations in resistance within the material stack being based on one of a plurality of resistive states of the variable resistive layer. The method also includes generating two magnetic fields within a transformer, the transformer being operatively coupled to the first and second conductive contact layers and generating a differential output signal within the transformer based on the two magnetic fields, the differential output signal being associated with one of the plurality of resistive states.

Transformer for determining the state of a variable resistive layer in a material stack

An embodiment may be described as a switched capacitor analog equalizer circuit with offset voltage cancellation, where an embodiment comprises an amplifier in which a feedback path from its output port to one of its input ports is provided during a reset phase, and where the amplifier's input port connected to the feedback path is also connected to one terminal of an offset-correction capacitor and one terminal of a sampling capacitor. The other terminal of the offset-correction capacitor is connected to a switch and the other terminal of the sampling capacitor is connected to an input port to receive a signal. During the reset phase, the switch is open, and during a sampling phase, the switch is closed so that the offset-correction capacitor and the sampling capacitor are connected in parallel. Other embodiments are described and claimed.

Switched capacitor equalizer with offset voltage cancelling

In an embodiment, an analog voltage recovery circuit comprising a plurality of capacitors having first terminals connected to a node having the analog voltage, and comprising a state machine, where during an operating mode the second terminals of the plurality of capacitors are coupled to a first rail, and where during a digitization mode the state machine couples the second terminals of a set of the plurality of capacitors to a second rail so that the analog voltage is closer to the second rail voltage than during the beginning of the digitization mode. In an embodiment, the analog voltage recovery circuit brings the node voltage to the second rail voltage at the end of the digitization mode, and then floats the node and couples the second terminals of the plurality of capacitors to the first rail to approximately restore the analog voltage. Other embodiments are described and claimed.

Analog voltage recovery circuit

In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.

Self-correcting buffer

A switched-capacitor circuit that may be used for equalization, but configurable for voltage margining. The switched-capacitor circuit cancels the offset voltage inherent in an amplifier and sets the common mode of an input signal at half the rail voltage. Two capacitors level shift an input signal before being applied to the two input ports of an amplifier. When used for voltage margining, the input voltage swing is reduced at the input ports of the amplifier by connecting a digital-to-analog controlled voltage source to the two capacitors.

Growing community of inventors

Queen Creek, AZ, United States of America

Luke A Johnson