Nxp B.v.

U.S. Philips Corporation

Koninklijke Philips Corporation N.v.

Jds Uniphase Corporation

Lukas Frederik Tiemeijer

Remigius S Van Roemburg

Coen T Liedenbaum

John J Reid

Raymond Van Roijen

Petrus J Thijs

Engelbertus C Pennings

Bastiaan H Verbeek

Johan Hendrik Klootwijk

Freddy Roozeboom

Mark Pieter Van Der Heijden

Derk Reefman

Nenad Pavlovic

Jozef Reinerus Maria Bergervoet

Jaap Ruigrok

Viet Thanh Dinh

Maristella Spella

Josephus Henricus Bartholomeus Van Der Zanden

Vittorio Cuoco

Xin Yang

Waqas Hassan Syed

Rob Mathijs Heeres

Edwin Van Der Heijden

Maarten Lont

Johannes J Binsma

Willem Schouten

Harish Nandagopal

Alexé Levan Nazarian

Marnix Bernard Willemsen

Bartholomeus Wilhelmus Christiaan Hovens

Cornelis M Groeneveld

Ralf Maria Theodoor Pijper

Alessandro Baiano

Jan Anne Van Steenwijk

Hugo Veenstra

Valerie Marthe Girault

Sven Walczyk

Dominicus M W Leenaerts

Ramon J Havens

A metal oxide semiconductor, MOS, device () is described that includes a gate terminal, at least one source terminal and at least one drain terminal, wherein at least one source terminal and at least one drain terminal are formed of metal and are connected to a number of respective contact vias. A plurality of local interconnect layers, LIL, () are connected respectively to the least one source terminal and at least one drain terminal through the number of respective contact vias, wherein the at least one source terminal and the at least one drain terminal respectively connected to the plurality of LIL () are configured such that: the at least one source terminal and the at least one drain terminal do not overlap in a first direction () and a second direction () that is orthogonal to the first direction (); and the at least one source terminal and the at least one drain terminal do not overlap or only a proportion of the at least one source terminal and the at least one drain terminal overlap in a third direction (), where the third direction () is orthogonal to both the first direction () and the second direction ().

Metal oxide semiconductor device

A compact planar balun formed on a substrate including a hairpin-shaped conductive microstrip and a single-ended contact. The hairpin-shaped conductive microstrip includes first and second linear segments integrally formed with a U-shaped segment, and a single-ended contact is conductively coupled at a location along the first linear segment. The first and second linear segments each have a first characteristic impedance and are in parallel with each other having a first end forming first and second differential contacts and having a second end. The U-shaped segment has a second characteristic impedance that is less than the first characteristic impedance in order to achieve proper scatter parameter alignment. The U-shaped segment may be generally formed thicker or wider than the linear segments to achieve a reduced characteristic impedance. In the alternative or in addition, co-planer ground metal is formed closer to the U-shaped segment to achieve a reduced characteristic impedance.

Planar balun with non-uniform microstrip line width to improve S-parameter alignment

An integrated circuit transformer () is formed with a primary winding () located in at least a first winding layer having a first thickness, a secondary winding () located in at least the first winding layer and having a first center point at the first side of the transformer and two secondary terminals at a second, opposite side of the transformer, and a first center tap feed line () located along a symmetry axis of the transformer in an upper metal layer having a second thickness that is at least equivalent to the first thickness of the first winding layer, wherein the first center tap feed line has a direct electrical connection to the first center point in the secondary winding.

High current integrated circuit-based transformer

A Field Effect Transistor (FET) capable of operating at high frequencies and includes comb-shaped source and drain electrodes. The comb-shaped drain electrode includes a plurality of thin comb-shape drain electrode layers at corresponding levels of the FET, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped drain electrodes of each other layer. The comb-shaped source electrode includes a plurality of comb-shape source electrode layers at the corresponding levels, each comb-shaped drain electrode layer including a plurality of drain electrode fingers having substantially the same width as the comb-shaped source electrodes of each other layer. In addition, the inter-level retraction of adjacent drain electrode layers is the same or substantially the same. Similarly, the inter-level retraction of adjacent source electrode layers is the same or substantially the same.

Field effect transistor and method of making

An apparatus, method and package for electronic tamper detection. In one example, an apparatus, device or package for electronic tamper detection includes: a first inductor positioned at a first distance from a first conductive surface; a first oscillator generating a first frequency in dependence upon the first inductor; and a comparator setting a tamper detected status if the generated first frequency is not within an error tolerance to a pre-stored first frequency. One example of a method for fabricating an electronic tamper detection apparatus, device, or package is also provided.

Electronic tamper detection

An integrated circuit based transformer, comprising: a primary winding located in a winding layer, the primary winding having two primary terminals at a first side of the transformer; a secondary winding located in a winding layer, the secondary winding having two secondary terminals at a second side of the transformer, the first and second sides located at different sides of the transformer; and a reference bar located in a reference bar layer, the reference bar having a primary reference bar terminal at the first side of the transformer, and having a secondary reference bar terminal at the second side of the transformer. The reference bar is configured to provide a direct electrical connection between the first reference bar terminal and the second reference bar terminal.

Integrated circuit based transformer

A compensation network for a radiofrequency transistor is disclosed. The compensation network comprises first and second bonding bars for coupling to a first terminal of the RF transistor and a compensation capacitor respectively; one or more bond wires coupling the first and second bonding bars together; and a compensation capacitor formed from a first set of conductive elements coupled to the second bonding bar, the first set of conductive elements interdigitating with a second set of conductive elements coupled to a second terminal of the RF transistor.

Compensation network for RF transistor

The invention relates to a field-effect transistor having a higher efficiency than the known field-effect transistors, in particular at higher operating frequencies. This is achieved by electrically connecting sources of a plurality of main current paths by means of a strap line (SL) being inductively coupled to a gate line (Gtl) and/or a drain line (Drnl) for forming an additional RF-return current path parallel to the RF-return current path in a semiconductor body (SB). The invention further relates to a field-effect transistor package, a power amplifier, a multi-stage power amplifier and a base station comprising such a field-effect transistor.

High frequency field-effect transistor

Capacitive circuits are implemented with desirable quality factors in various implementations. According to an example embodiment, a fringe capacitor includes two capacitive circuits (e.g., plates), respectively having a plurality of capacitive fingers extending from an end structure, and respectively having a connecting pin that is adjacent the connecting pin of the other capacitive circuit, on a common side fringe capacitor. The capacitive fingers are arranged in stacked layers, with vias connecting the fingers in different layers back to the connecting pins.

Fringe capacitor circuit

A planar inductive unit having at least one operating frequency is provided. The inductive unit comprises at least one inductor winding () having a first width () and a centre () and being arranged in a first plane. The inductive unit furthermore comprises at least one ground path () having a first section () extending in the first plane and at least a second section () with a second width () extending in at least a second plane.

Planar inductive unit and an electronic device comprising a planar inductive unit

The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. In many applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 &#x3bc;H, and must have an equivalent series resistance of less than 0.1&#x3a9;. For this reason, those inductors are always bulky components, of a typical size of 2&#xd7;2&#xd7;1 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 very-high DC resistance values.

Planar, monolithically integrated coil

A planar inductor () comprises a conductive path in the form of a spiral pattern (A-D,A-D). A conductive connecting path (A,) connects a terminal () to an intermediate tap point (A). The connecting path comprises at least one path portion which is radially directed with respect to the spiral pattern (A-D). The connecting path (A,) can be routed via the inside of the spiral pattern. Where the connecting path comprises only radially-directed path portions, they are commonly joined at the center () of the spiral pattern. Multiple path portions (A,B) can each connect to the intermediate tap point of a respective conductive path. The connecting path can use a further conductive track () which is parallel to the conductive path which forms the spiral pattern.

Planar inductor

An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections.

Inductor

An RF field effect transistor has a gate electrode, and comb shaped drain and source electrodes, fingers of the comb shaped drain being arranged to be interleaved with fingers of the source electrode, the source and drain electrodes having multiple layers (). An amount of the interleaving is different in each layer, to enable optimization, particularly for low parasitic capacitance without losing all the advantage of low current density provided by the multiple layers. The interleaving is reduced for layers further from the gate electrode by having shorter fingers. The reduction in interleaving can be optimized for minimum capacitance, by a steeper reduction in interleaving, or for minimum lateral current densities in source and drain fingers, by a more gradual reduction in interleaving. This can enable operation at higher temperatures or at higher input bias currents, while still meeting the requirements of electro-migration rules.

High frequency transistor layout for low source drain capacitance

The invention relates to a planar inductive component () comprising at least a first and a second concentric inductor, which include a first and a second spiral pattern (A,B), respectively. Both spiral patterns have a first end point (A,B) and a second end point (A,B), are electrically interconnected, interlaced, and interrupted at the outer side, and provided with two contacts (A,B) on one side of the opening (A,B) and two contacts (A,B) on the other side of the opening (A,B). By interconnecting the first two contacts (A,B) and the second two contacts (A,B), respectively, both spiral patterns are connected in parallel. The spiral patterns (A,B), which are magnetically coupled, have identical electrical and magnetic properties. This leads to a reduction of eddy current losses at high frequencies. This results in a planar inductive component () which is suitable for high-frequency operation with a high maximum quality factor Q. The invention also relates to a planar transformer comprising two planar inductive components according to the invention. The first planar inductive component serves as the first winding of the planar transformer; the second planar inductive component serves as the second winding of the planar transformer. As a result of the above-mentioned reduction in eddy current losses at high frequencies, the planar transformer can suitable be used for high-frequency operation.

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Eindhoven, Netherlands

Lukas Frederik Tiemeijer