Western Digital Technologies, Inc.

Hgst Netherlands, B.v.

Hitachi Global Storage Technologies Netherlands B.v.

Sandisk Technologies Inc.

Other

Rambus Inc.

Lattice Semiconductor Corporation

Luiz M Franca-Neto

Zvonimir Z Bandic

Cyril Guyot

Robert Eugeniu Mateescu

John Thomas Contreras

Bernhard E Knigge

Jordan Asher Katine

Qingbo Wang

Richard Leo Galbraith

Jeffrey Scott Lille

Neil Leslie Robertson

Travis Roger Oenning

Jeffery Robinson Childress

Mac D Apodaca

Hessam Mahdavifar

Christopher John Petti

Petrus Antonius Van Der Heijden

Ricardo Ruiz

Viacheslav Anatolyevich Dubeyko

Bruce Alvin Gurney

Kurt A Rubin

Peter Michael Baumgart

Luis Vitorio Cargnini

Erhard Theodor Schreck

Stefan Maat

Frank Lambrecht

Bruno Jean Marchon

Dejan Vucinic

Lidu Huang

Jr-Yi Shen

Stephen Paul Williams

Timothy Tsai

Gurinder P Singh

Adam Manzanares

Frank R Chu

Vijay P S Rawat

Martin Yu-Wen Chen

Richard Kroeker

Marta A G Da Franca

Embodiments of storage device architecture for processing data using machine learning are disclosed. In some embodiments, the storage device includes a separate I/O core and a neural network core. The storage device can create a copy of data streams in which the data is stored, and the neural network core can process the copy of the data streams in a neural network while the I/O core can perform read or write functions on the data streams.

Enhanced storage device memory architecture for machine learning

Some embodiments include a special-purpose hardware accelerator that can perform specialized machine learning tasks during both training and inference stages. For example, this hardware accelerator uses a systolic array having a number of data processing units ('DPUs') that are each connected to a small number of other DPUs in a local region. Data from the many nodes of a neural network is pulsed through these DPUs with associated tags that identify where such data was originated or processed, such that each DPU has knowledge of where incoming data originated and thus is able to compute the data as specified by the architecture of the neural network. These tags enable the systolic neural network engine to perform computations during backpropagation, such that the systolic neural network engine is able to support training.

Reconfigurable systolic neural network engine

Devices and methods for systolically processing data according to a neural network. In one aspect, a first arrangement of processing units includes at least first, second, third, and fourth processing units. The first and second processing units are connected to systolically pulse data to one another, and the third and fourth processing units are connected to systolically pulse data to one another. A second arrangement of processing units includes at least fifth, sixth, seventh, and eighth processing units. The fifth and sixth processing units are connected to systolically pulse data to one another, and the seventh and eighth processing units are connected to systolically pulse data to one another. The second processing unit is configured to systolically pulse data to the seventh processing unit along a first interconnect and the third processing unit is configured to systolically pulse data to the sixth processing unit along a second interconnect.

Systolic neural network engine with crossover connection optimization

A method of performing computations of a neural network is disclosed comprising assigning a first processing unit to perform computations of a first node of a first layer of the neural network and assigning a second processing unit to perform computations of a second node of a second layer of the neural network. Computations of the first node are performed using the first processing unit to generate a first activation output that is transmitted to a first output systolic element of the first processing unit. The first activation output is systolically pulsed to a first input systolic element of the second processing unit and computations of the second node are performed by using the second processing unit to process at least the first activation output.

Systolic neural network engine capable of forward propagation

Devices and methods for performing computations of a neural network include determining, for a particular layer of the neural network, a number of input channels and a number of output maps generated for particular pixels of a plurality of pixels. A portion of a processing chip is configured into a plurality of processing units, with the processing chip including a plurality of tensor arrays and a plurality memory cells. A particular processing unit of the plurality of processing units performs computations associated with a particular pixel. Individual processing units of the plurality of processing units each include a number of tensor arrays determined based on the number of input channels and a number of memory cells or pixel arrays corresponding to a number of output maps. The plurality of processing units is assigned to perform computations of the particular layer.

Configurable neural network engine of tensor arrays and memory cells

A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.

Systolic neural network engine capable of backpropagation

Configurable neural network engine for convolutional filter sizes

Embodiments of an improved memory architecture for processing data inside of a device are described. In some embodiments, the device can store neural network layers, such as a systolic flow engine, in non-volatile memory and/or a separate first memory. A processor of a host system can delegate the execution of a neural network to the device. Advantageously, neural network processing in the device can be scalable, with the ability to process large amounts of data.

Enhanced memory device architecture for machine learning

Embodiments of the present disclosure generally relate to a cloud computing network and a method of transferring information among processing nodes in a cloud computing network. In one embodiment, a cloud computing network is disclosed herein. The cloud computing network includes a plurality of motherboards arranged in racks. Each individual motherboard includes a central hub and a plurality of processing nodes equipped to the central hub. Each processing node is configured to access memory or storage space of another processing node in the same motherboard by intermediation of the hub. The access is called a communication between a pair of processing nodes. The communication includes a string of information transmitted between processing nodes. The string of information has a plurality of frames. Each frame includes a plurality of time slots, wherein each time slot is allotted a specific node pair.

All-connected by virtual wires network of data processing nodes

Devices and methods for systolically processing data according to a neural network. A first processing unit performs computations of a first node of a first layer to generate a first output and attaches a first tag to the first output identifying the first processing unit. A second processing unit performs computations of a second node of the first layer to generate a second output and attaches a second tag to the second output identifying the second processing unit. A third processing unit performs computations of a third node of a second layer including receiving the first and second outputs, using a first convolutional engine to perform a first convolution on the first output using a first weight identified by the first tag, and using a second convolutional engine of to perform a second convolution on the second output using a second weight identified by the second tag.

Convolution engines for systolic neural network processor

At least a subset of first processing units of a first arrangement of a first systolic processing chip is assigned to a first layer of a neural network and at least a subset of second processing units of a second arrangement of the first systolic processing chip is assigned to a second layer of the neural network. At least a subset of third processing units of a third arrangement of a second systolic processing chip is assigned to a third layer of the neural network. Input data is processed using the subset of the first processing units to generate first activation output values. The first activation output values are systollically pulsed to the subset of the second processing units and processed to generate second activation output values. The second activation output values are processed using the subset of the third processing units of the second systolic processing chip.

Multi-core systolic processor system for neural network processing

At least a subset of first processing units of a first arrangement of an array of processing units is assigned to perform computations of a first layer of a neural network and at least a subset of second processing units of a last arrangement is assigned to perform computations of a second layer. At least a second subset of the first processing units of the first arrangement is re-assigned to perform computations of a third layer. In one aspect, it is determined that a number of layers exceeds a number of arrangements of processing units of a systolic processing chip. A first arrangement of processing units of the number of arrangements is assigned to perform computations according to a first layer for a first set of forward propagations, and the first arrangement is assigned to perform computations according to a different layer for a second set of forward propagations.

Systolic neural network processor with feedback control

Embodiments of an improved memory architecture by processing data inside of the memory device are described. In some embodiments, the memory device can store neural network layers, such as a systolic flow engine, in non-volatile memory and/or a separate DRAM memory. Central processing unit (CPU) of a host system can delegate the execution of a neural network to the memory device. Advantageously, neural network processing in the memory device can be scalable, with the ability to process large amounts of data.

A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Apparatus and method for low power low latency high capacity storage class memory

Adjusting enhancement coefficients for neural network engine

Growing community of inventors

Sunnyvale, CA, United States of America

Luiz M Franca-Neto