Cray Incorporated

Hewlett Packard Enterprise Development LP

Luiz DeRose

Heidi Lynn Poxon

Sanyam Mehta

James Robert Kohn

Daniel Jonathan Ernst

Clayton D Andreasen

David W Oehmke

William Homer

John Levesque

Brian H Johnson

Dean T Johnson

A parallelization assistant tool system to assist in parallelization of a computer program is disclosed. The system directs the execution of instrumented code of the computer program to collect performance statistics information relating to execution of loops within the computer program. The system provides a user interface for presenting to a programmer the performance statistics information collected for a loop within the computer program so that the programmer can prioritize efforts to parallelize the computer program. The system generates inlined source code of a loop by aggressively inlining functions substantially without regard to compilation performance, execution performance, or both. The system analyzes the inlined source code to determine the data-sharing attributes of the variables of the loop. The system may generate compiler directives to specify the data-sharing attributes of the variables.

Assisting parallelization of a computer program

A system is provided for allocating memory for data of a program for execution by a computer system with a multi-tier memory that includes LBM and HBM. The system accesses a data structure map that maps data structures of the program to the memory addresses within an address space of the program to which the data structures are initially allocated. The system executes the program to collect statistics relating to memory requests and memory bandwidth utilization of the program. The system determines an extent to which each data structure is used by a high memory utilization portion of the program based on the data structure map and the collected statistics. The system generates a memory allocation plan that favors allocating data structures in HBM based on the extent to which the data structures are used by a high memory utilization portion of the program.

Memory allocation system for multi-tier memory

A method for prefetching data into a cache is provided. The method allocates an outstanding request buffer ('ORB'). The method stores in an address field of the ORB an address and a number of blocks. The method issues prefetch requests for a degree number of blocks starting at the address. When a prefetch response is received for all the prefetch requests, the method adjusts the address of the next block to prefetch and adjusts the number of blocks remaining to be retrieved and then issues prefetch requests for a degree number of blocks starting at the adjusted address. The prefetching pauses when a maximum distance between the reads of the prefetched blocks and the last prefetched block is reached. When a read request for a prefetched block is received, the method resumes prefetching when a resume criterion is satisfied.

High-bandwidth prefetcher for high-bandwidth memory

Systems and methods provide a display indicating performance characteristics of a computer application. The display may include a call graph having nodes that represent subunits of the application. A first set of statistics for the subunit may be represented in the size or dimensions of the node. A second set of statistics may be displayed in the interior of the node. A third set of statistics may be displayed in response to selecting the node.

Performance visualization including hierarchical display of performance data

Growing community of inventors

Rosemount, MN, United States of America

Luiz DeRose