International Business Machines Corporation

Luiz Carlos Alves

Patrick James Meaney

William J Clarke

Luis Alfonso Lastras-Montano

K Paul Muller

Timothy Jay Dell

Eldee Stephens

Warren Edward Maule

Kevin Charles Gower

William Vincent Huott

Robert Brett Tremaine

Sanjeev Ghai

Christopher W Steffen

Barry Marshall Trager

Scott Barnett Swaney

Mark Andrew Brittain

Kevin W Kark

Thomas J Knips

Christopher Raymond Conklin

Gary Alan Peterson

Christopher N Oelsner

Daniel Francis Casper

James A O'Connor

Steven G Glassen

Daniel J Stigliani, Jr

Thomas J Dewkett

A technique relates to dynamic time-domain reflectometry (TDR). A machine spares a bad lane in a bus. The bad lane is taken offline. TDR is dynamically executed on the bad lane while the bus is still in operation. A defect is isolated using results of the TDR.

Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system

Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Built-in testing of unused element on chip

A field programmable gate array (FPGA) includes configuration RAM (CRAM) including at least one non-hardened portion and at least one hardened portion having an SER resilience greater than an SER resilience of the non-hardened portion.

Soft error resilient FPGA

Error correction and detection in a redundant memory system including a a computer implemented method that includes receiving data including error correction code (ECC) bits, the receiving from a plurality of channels, each channel comprising a plurality of memory devices at memory device locations. The method also includes computing syndromes of the data; receiving a channel identifier of one of the channels; and removing a contribution of data received on the channel from the computed syndromes, the removing resulting in channel adjusted syndromes. The channel adjusted syndromes are decoded resulting in channel adjusted memory device locations of failing memory devices, the channel adjusted memory device locations corresponding to memory device locations.

RAIM system using decoding of virtual ECC

Correcting memory device (chip) and memory channel failures in the presence of known memory device failures. A memory channel failure is located and corrected, or alternatively up to c chip failures are corrected and up to d chip failures are detected in the presence of up to u chips that are marked as suspect. A first stage of decoding is performed that results in recovering an estimate of correctable errors affecting the data or in declaring an uncorrectable error state. When an uncorrectable error state is declared, a second stage of decoding is performed to attempt to correct u erasures and a channel error in M iterations where the channel location is changed in each iteration. A correctable error is declared in response to exactly one of the M iterations being successful.

Correcting memory device and memory channel failures in the presence of known memory device failures

Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.

Error correction and detection in a redundant memory system

A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.

System and method for providing a high fault tolerant memory system

A method and system is presented for correcting a data error in a primary Dynamic Random Access Memory (DRAM) in a Dual In-line Memory Module (DIMM). Each DRAM has a left half (for storing bits) and a right half (for storing bits). A determination is made as to whether the data error was in the left or right half of the primary DRAM. The half of the primary DRAM in which the error occurred is removed from service. All subsequent reads and writes for data originally stored in the primary DRAM's defective half are made to a half of a spare DRAM in the DIMM, while the DRAM's non-defective half continues to be used for subsequently storing data.

Double DRAM bit steering for multiple error corrections

A system, method and storage medium for providing redundant I/O access between a plurality of interconnected processor nodes and I/O resources. The method includes determining whether a primary path between the interconnected processor nodes and the I/O resources is operational, where the primary path includes a first processor node and a primary multiplexer. If the primary path is operational, the transactions are routed via the primary path. If the primary path is not operational, the transactions are routed between the interconnected processor nodes and the I/O resources via an alternate path that includes a second processor node and an alternate multiplexer.

Method, system and storage medium for redundant input/output access

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Hopewell Junction, NY, United States of America

Luiz Carlos Alves