Hewlett-Packard Development Company, L.p.

Google Inc.

Exaflop LLC

Luiz Andre Barroso

Kourosh Gharachorloo

Wolf-Dietrich Weber

Andreas Georg Nowatzyk

Robert J Stets, Jr

Xiaobo Fan

Mosur Kumaraswamy Ravishankar

Daniel J Scales

James Laudon

William Riis Hamburgen

Jimmy Clidaras

Andrew B Carlson

Michael Roger Marty

Jeffrey Adgate Dean

Christopher Gregory Malone

Sanjay Ghemawat

Monika Hildegard Henzinger

Michael C Ryan

Taliver Heath

Benjamin Thomas Smith

Deborah Anne Wallach

Nathaniel Edward Pettis

Andrew H Tibbits

Eduardo Pinheiro

Stephanie Hua Taylor

A method of designing a data center can include determining a design power density, determining an oversubscription ratio, and determining a spatial layout of the data center using the design power density and the oversubscription ratio. The design power density can be in units of power per unit length.

Data center design

A method for use in deploying computers into a data center includes calculating in a computer an expected peak power draw for a plurality of computers. The expected peak power draw for the plurality of computers is less than a sum of individual expected peak power draws for each computer from the plurality of computers.

Computer and data center load determination

A method includes performing one or more operations as requested by a thread executing on a processor, the thread having a thread context; receiving a park request from the thread, the park request received following a request from the thread for a low latency resource, wherein the cache response time is less than or equal to a resource response threshold so as to allow the thread context to be stored and retrieved from the cache in less time than the portion of time it takes to complete the request for the low latency resource; storing the thread context in the cache; detecting that the resume condition has occurred; retrieving the thread context from the cache; and resuming execution of the thread.

Low latency thread context caching

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated cores. In one aspect, a method includes a multi-core processor having n cores, including, selecting k cores of the n cores of the multi-core processor to perform dedicated low-latency operations for the n-core processor, where k is less than n, m cores are unselected, and each core of the multi-core processor has a rated core capacity. The methods operate the selected k cores at less than the rated core capacity such that k cores are collectively underutilized by an underutilized capacity and operate one or more of the m cores at a capacity in excess of the rated core capacity such that the m cores operate at a collective capacity that exceeds a collective capacity of the rated core capacities of the m cores.

Modulating processsor core operations

Techniques for managing power loads of a data center include electrically coupling a data center infrastructure power load and a data center IT power load in a power distribution system having a specified power capacity, the infrastructure power load including a plurality of infrastructure power loads associated with at least one of a data center cooling system, a data center lighting system, or a data center building management system, and the IT power load including a plurality of IT power loads associated with a plurality of rack-mounted computing devices; determining that a predicted amount of the IT power load is about equal to or greater than a threshold power value; throttling the infrastructure power load to reduce a portion of the power capacity used by the infrastructure power load; and based on throttling the infrastructure power load, increasing another portion of the power capacity available to the IT power load.

Managing power between data center loads

A method includes deploying non-volatile random access memory (NVRAM) in a memory arrangement coupled to a CPU core of a computing device via a memory bus. The method further includes configuring the CPU core to conduct NVRAM read operations directly over the memory bus, and providing an I/O logic device to process write instructions initiated by the CPU core as a Direct Memory Access (DMA) write operation on the NVRAM.

Non-volatile random access memory in computer primary memory

A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit.

Shared input/output (I/O) unit

A method of monitoring power load of a data center includes monitoring a power usage of a cluster of the data center, monitoring a power usage of a power distribution unit (PDU) of the data center, and monitoring a power usage of at least one of a rack of the data center or a computer within a rack of the data center.

Data center load monitoring for utilizing an access power amount based on a projected peak power usage and a monitored power usage

A method of controlling power usage in a data center includes monitoring a power usage of a plurality of computers in the data center, generating a signal indicating that the power usage is within a threshold of a maximum power capacity, and in response to the signal, adjusting performance of at least one computer in the plurality of computers.

Load control in a data center

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Mountain View, CA, United States of America

Luiz Andre Barroso