Western Digital Technologies, Inc.

Luis Vitorio Cargnini

Viacheslav Anatolyevich Dubeyko

Zvonimir Z Bandic

Dejan Vucinic

Luiz M Franca-Neto

Kurt A Rubin

Qingbo Wang

In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.

Processor in non-volatile storage memory

A Memory Device (MD) for storing temporary data designated for volatile storage by a processor and persistent data designated for non-volatile storage by the processor. An address is associated with a first location in a volatile memory array and with a second location in a Non-Volatile Memory (NVM) array of the MD. Data is written in the first location, and flushed from the first location to the second location. A refresh rate for the first location is reduced after flushing the data from the first location until after data is written again to the first location. In another aspect, a processor designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.

Volatility management for memory device

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

Fabric interconnection for memory banks based on network-on-chip methodology

Embodiments disclosed herein generally relate to the use of Network-on-Chip architecture for solid state memory structures, both volatile and non-volatile, which provide for the access of memory storage blocks via a router. As such, data may be sent to and/or from the memory storage blocks as data packets on the chip. The Network-on-Chip architecture may further be utilized to interconnect unlimited numbers of memory cell matrices, spread on a die, thus allowing for reduced latencies among matrices, selective power control, unlimited memory density growth without major latency penalties, and reduced parasitic capacitance and resistance. Other benefits may include improved signal integrity, larger die areas available to implement memory arrays, and higher frequency of operation.

At least a subset of first processing units of a first arrangement of an array of processing units is assigned to perform computations of a first layer of a neural network and at least a subset of second processing units of a last arrangement is assigned to perform computations of a second layer. At least a second subset of the first processing units of the first arrangement is re-assigned to perform computations of a third layer. In one aspect, it is determined that a number of layers exceeds a number of arrangements of processing units of a systolic processing chip. A first arrangement of processing units of the number of arrangements is assigned to perform computations according to a first layer for a first set of forward propagations, and the first arrangement is assigned to perform computations according to a different layer for a second set of forward propagations.

Systolic neural network processor with feedback control

In some implementations, a computing system is provided. The computing system includes a device. The device includes a non-volatile memory divided into a plurality of memory sub-arrays. Each memory sub-array comprises a plurality of selectable locations. A plurality of data processing units are communicatively coupled to the non-volatile memory in the absence of a central processing unit of the computing system. The data processing unit is assigned to process data of a memory sub-array, and configured to store the first data object in the non-volatile memory receive a first data object via a communication interface. The first data object comprises a first content and is associated with a first set of keywords. The data processing unit is also configured to add the first set of keywords to a local dictionary. The local dictionary is stored in the non-volatile memory. The data processing unit is further configured to determine whether the first data object is related to one or more other data objects. The data processing units is further configured to create one or more relationships between the first data object and the one or more other data objects in response to determining that the first data object is related to one or more other data objects.

Neural networks using data processing units

A processor includes processor memory arrays including one or more volatile memory arrays and one or more Non-Volatile Memory (NVM) arrays. Volatile memory locations in the one or more volatile memory arrays are paired with respective NVM locations in the one or more NVM arrays to form processor memory pairs. Process data is stored for different processes executed by at least one core of the processor in respective processor memory pairs. Processes are executed using the at least one core to directly access the process data stored in the respective processor memory pairs.

Processor with processor memory pairs for improved process switching and methods thereof

A system and method for allocating memory to a heterogeneous address space includes identifying, by an operating system, at least one superset feature from an application configured to be executed on a host device. The address space associated with the application includes a plurality of supersets, and wherein the operating system allocates the memory to each of the plurality of supersets from a non-volatile memory or a volatile memory based upon the at least one superset feature.

Systems and methods for heterogeneous address space allocation

A Memory Device (MD) includes a Non-Volatile Memory (NVM) including a first memory array and a second memory array. An address is associated with a first location in the first memory array and with a second location in the second memory array. A read command is received to read data for the address, and it is determined whether data stored in the NVM for the address is persistent. If not, it is determined whether data for the address has been written for the address after a last power-up of the MD. The read command is performed by returning zeroed data if data has not been written for the address after the last power-up. If data has been written after the last power-up, data stored in the first location is returned. In one aspect, a processor sends a command to the MD setting a volatility mode for the MD.

Volatility management for non-volatile memory device

A memory system includes a memory having a first executable memory cell and a compilation unit. The compilation unit is configured to receive a sequence of instructions from a host device, convert each of the sequence of instructions into an execution stream, load a first code from the execution stream into a code portion of the first executable memory cell and load a first data from the execution stream into a data portion of the first executable memory cell. The first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.

Executable memory cell

A computing unit includes a data processing unit having a plurality of executable memory cells. Each of the plurality of executable memory cells includes a code portion for storing code, a data portion for storing data, and an arithmetic and logic unit for applying the code to the data. The computing system also includes a compilation unit for converting a sequence of instructions into an execution stream. The execution stream includes the code and the data that is executed by the plurality of executable memory cells.

Executable memory cells

A Memory Device (MD) includes a configurable Non-Volatile Memory (NVM) including a first memory array and a second memory array. The configurable NVM stores temporary data designated for volatile storage by a Central Processing Unit (CPU) and persistent data designated for non-volatile storage by the CPU. An address is associated with a first location in the first memory array and with a second location in the second memory array. In performing a command to write data for the address, it is determined whether to write the data in the second location based on a volatility mode set for the MD. According to another aspect, a CPU designates a memory page in a virtual memory space as volatile or non-volatile based on data allocated to the memory page, and defines the volatility mode for the MD based on whether the memory page is designated as volatile or non-volatile.

Systems and methods are disclosed for recovering from various types of data and process corruptions at a data processing unit of a plurality of data processing units each coupled with a non-volatile memory divided into a plurality of selectable locations, in a system absent a central processing unit. In some embodiments a data processing unit is configured to determine validity of an allocation table of the data processing unit, retrieve a process descriptor from the allocation table, parse the non-volatile memory for a first set of process data corresponding to the process descriptor, determine validity of the first set of process data corresponding to the process descriptor and attempt to recover the first set of process data in accordance with a determination that the first set of process data is invalid.

Methods, systems and devices for recovering from corruptions in data processing units in non-volatile memory devices

Systems and methods are disclosed for maintaining a status of a respective data processing unit (DPU) of a plurality of data processing units, each coupled to non-volatile memory. In some embodiments a first DPU is configured to execute one or more persistent processes, wherein the one or more processes persist in the non-volatile memory over power cycles, generate a first broadcast message upon completion of a first persistent process, transmit the first broadcast message to a set of DPUs associated with monitoring the first DPU, receive a second broadcast message from a second DPU of the set of DPUs and assign a value indicating an active status for the second DPU in a status table to track the status of each DPU of the set of DPUs.

Growing community of inventors

San Jose, CA, United States of America

Luis Vitorio Cargnini