Infineon Technologies Ag

Infineon Technologies Austria Ag

Luis Hernandez-Corporales

Andreas Wiesbauer

Cesare Buffa

Andres Quintero Alonso

Carlos Andres Perez Cruz

Fernando Cardes Garcia

Ruben Garvi Jimenez-Ortiz

Pedro Augusto Borrego Lambin Torres Amaral

Enrique Prefasi

Bernhard Kuttin

Guillermo Alejandro Lopez Fernandez

Victor Medina

Francois Marie Leger

Andrés Quintero Alonso

Javier Granizo Cuadrado

A circuit includes: a micro-electromechanical system (MEMS) microphone configured to generate a voltage signal at an output terminal of the MEMS microphone in response to a sound signal; a voltage-controlled-oscillator (VCO) coupled to the output terminal of the MEMS microphone and configured to output, at an output terminal of the VCO, a frequency modulated signal having a frequency proportional to the voltage signal; a frequency-to-digital (FTD) converter coupled to the output terminal of the VCO and configured to convert the frequency modulated signal into a digital output signal proportional to the frequency; a frequency-to-voltage (FTV) conversion circuit coupled to the output terminal of the VCO and configured to generate a bias voltage at an output terminal of the FTV conversion circuit in accordance with the frequency modulated signal; and a resistor coupled between the output terminal of the MEMS microphone and the output terminal of the FTV conversion circuit.

Operation point stabilization for VCO-ADC using switched-capacitor frequency-to-current conversion

A voltage-controlled oscillator analog-to-digital converter (VCO-ADC) includes a first source follower coupled between a first input terminal and a first internal node; a first VCO having an input coupled to a second internal node; a first variable resistor coupled between the first internal node and the second internal node; and a digital signal processing component coupled between an output of the first VCO and a output terminal.

Power and signal-to-noise ratio regulation in a VCO-ADC

An analog-to-digital converter includes a voltage-controlled oscillator (VCO) having an input for receiving an analog input signal; a double binary counter having a first input coupled to a first output of the VCO, a second input coupled to a second output of the VCO; a first set of registers coupled to the first output of the double binary counter; a second set of registers coupled to the second output of the double binary counter; sense amplifiers coupled to the outputs of the VCO; and a correction component coupled to the first set of registers, the second set of registers, and the sense amplifiers, wherein the correction component generates a coarse count, a fine count, and combines the coarse count and the fine count to provide a digital output signal representative of the analog input signal.

Coarse-fine counting architecture for a VCO-ADC based on interlocked binary asynchronous counters

An analog-to-digital converter includes a ring oscillator having an input for receiving an analog signal, a coarse counter including a maximum length sequence generator having an input coupled to the output of the ring oscillator, a fine counter including a Johnson counter having an input coupled to the output of the ring oscillator, and a difference generator having a first input coupled to the output of the coarse counter, a second input coupled to the output of the fine counter, and an output for providing a digital signal corresponding to the analog signal.

Voltage controlled oscillator based analog-to-digital converter including a maximum length sequence generator

In accordance with an embodiment, a circuit includes a first oscillator having an oscillation frequency dependent on an input signal at a first input, where the first oscillator is configured to oscillate when an enable input is in a first state and freeze its phase or reduce its frequency when the enable input is in a second state. The circuit also includes a first time-to-digital converter having an input coupled to an output of the first oscillator, and a pulse generator having an input coupled to a first clock input of the circuit and an output coupled to the enable input of the first oscillator, where the pulse generator is configured to produce a pulse having pulse width less than a period of a clock signal at the first clock input.

System and method for an oversampled data converter

According to an embodiment, a capacitance determination circuit is provided comprising a voltage controlled oscillator configured to generate a frequency signal whose frequency depends on a control voltage supplied to the voltage controlled oscillator, a capacitor coupled to the voltage controlled oscillator wherein the control voltage depends on a voltage across the capacitor and a processing circuit configured to generate, based on the frequency signal generated by the voltage controlled oscillator over a time interval comprising at least one phase in which the capacitor is charged and comprising at least one phase in which the capacitor is discharged, an indication of the capacitance of the capacitor.

Capacitance determination circuit and method for determining a capacitance

An analog-to-digital converter includes a ring oscillator having an input for receiving an analog signal, a coarse Gray code counter having a first input coupled to a first output of the ring oscillator and a second input for receiving a clock signal, a fine counter having first inputs coupled to secondary outputs of the ring oscillator and a second input for receiving the clock signal, a first difference generator having an input coupled to the output of the coarse counter, a second difference generator having an input coupled to the output of the fine counter, and an adder having a first input coupled to the output of the first difference generator, a second input coupled to the output of the second difference generator, and an output for providing a digital signal corresponding to the analog signal.

Coarse-fine quantization architecture for multiphase VCO-based ADCs

In various embodiments, a circuit is provided. The circuit includes: a voltage biasing circuit coupled to a microelectro-mechanical system (MEMS) microphone sensor, the MEMS microphone sensor coupled to a driver circuit, and the driver circuit coupled to an oscillator-based ADC circuit. The oscillator-based ADC circuit may include an Nth order sigma-delta modulator, where N is an integer equal to or greater than 1.

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Madrid, Spain

Luis Hernandez-Corporales