Infineon Technologies Ag

Infineon Technologies Austria Ag

Lantiq Deutschland Gmbh

Maxlinear Asia Singapore Pte Ltd

Luis Hernandez

Andreas Wiesbauer

Dietmar Straeussnigg

Dietmar Straussnigg

Martin Clara

Antonio Di Giandomenico

Richard Gaggl

David San Segundo Bello

Daniel Mark

Susana Paton

Daniel Gruber

Wim Dehaene

Christian Reindl

Andres Quintero Alonso

Pedro Augusto Borrego Lambin Torres Amaral

Dietmar Sträussnigg

Susana Paton Alvarez

Jorg Daniels

Ruben Garvi Jimenez-Ortiz

Manuel Sanchez-Renedo

Stefan Matschitsch

Dietmar Straussnig

Fernando Cardes

Bernd Rainer

Antonia Di Giandomenico

Eric Fernandez-Gutierrez

Susana Paton-Alvarez

An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.

VCO-ADC with frequency-controlled switched-capacitor feedback for linearization

A MicroElectroMechanical System (MEMS) includes a MEMS device; a feature extraction component coupled to an output of the MEMS device, wherein the feature extraction component is configured to provide a plurality of features of an output signal of the MEMS device; and a low data rate interface coupled to the feature extraction components, wherein the low data rate interface is configured to transmit the plurality of features of the output signal of the MEMS device, and wherein a low data rate of the low data rate interface is determined by a number of the plurality of features transmitted, wherein the MEMS device, the feature extraction component, and the low data rate interface are packaged together in a semiconductor package.

Digital microphone with low data rate interface

A controlled oscillator Analog-to-Digital Converter (ADC) includes an analog interface configured for receiving an analog differential input signal, and configured for providing a differential control signal; first and second controlled oscillators configured for receiving the differential control signal; and a frequency-to-digital converter having a first input coupled to an output of the first controlled oscillator, a second input coupled to an output of the second controlled oscillator, and an output for providing a digital output signal proportional to the analog differential input signal, wherein the analog interface or at least one of the first and second controlled oscillators is configured for receiving at least one disturb signal to prevent locking between the first and second controlled oscillators.

Offset switching to prevent locking in controlled oscillator analog-to-digital converters

In accordance with an embodiment, a circuit includes an oscillator having an oscillation frequency dependent on an input signal, a digital accumulator having a first input coupled to an output of the oscillator, a digital-to-analog converter (DAC) coupled to an output of the digital accumulator, an analog loop filter coupled to an output of the digital-to-analog converter, and a comparison circuit having an input coupled to an output of the analog loop filter and an output coupled to a second input of the digital accumulator.

System and method for an oversampled data converter

This disclosure relates to dynamic element matching in delay line circuits to reduce linearity degradation and delay line mismatching.

Dynamic element matching for delay lines

Disclosed are techniques for reducing noise and providing conversion signals in electronic components, including pulse width modulation (PWM) oversampling converters, by performing signal conversion having finite impulse response (FIR) feedback. Implementations may reduce the sensitivity of the conversion process to jitter in the sampling clock, thereby reducing noise and providing conversion signals.

Signal conversion using finite impulse response feedback

Techniques for reducing quantization error in electronic components are described herein.

Quantization error reduction in PWM full-MASH converters

Techniques for reducing sampling error in electronic components are described herein.

Sampling error reduction in PWM-MASH converters

Implementations and embodiments of decoders, encoder/decoder systems and converters are depicted and described.

Decoding, encoding/decoding and converting

Techniques for converting signals using finite impulse response (FIR) feedback are described herein.

A multiple output time-to-digital converter (TDC) and an Analog-to-Digital Converter (ADC) incorporating the multiple output TDC is disclosed.

Multiple output time-to-digital converter

This disclosure relates to adjusting a limit cycle frequency of a pulse width modulation in an analog to digital converter as a function of an input signal level to increase dynamic range.

Increasing the dynamic range of pulse width modulation in analog to digital converters

Sigma-delta modulators and a method of modulating are disclosed in which a first sigma-delta modulator having a first quantizer is provided, and a second quantizer is also provided. At least a first node of the first sigma-delta modulator upstream of the first quantizer and a second node of the first sigma-delta modulator upstream of the first quantizer to the second quantizer are coupled together.

Growing community of inventors

Madrid, Spain

Luis Hernandez