Cadence Design Systems, Inc.

Luis Guerra E Silva

Joel Reuben Phillips

Luis Miguel Silveira

In one embodiment of the invention, a method for electronic circuit design is disclosed. The method includes analyzing a hierarchy of a netlist of a circuit to determine primary inputs and primary outputs of the circuit at an upper level, and internal vertices of the circuit at lower levels between the primary inputs and the primary outputs; forming a timing graph of the circuit including a plurality of timing delay edges representing timing delay between the primary inputs, the internal vertices and the primary outputs to form a plurality of paths of a path space from the primary inputs to the primary outputs; and in response to the timing delay of the plurality of timing delay edges, dynamically pruning paths of the plurality of paths using branch and bound techniques on bounds of timing delay that are a function of one or more circuit parameters to reduce the path space down to one or more critical timing paths of the circuit with a worse case metric of timing delay between the primary inputs and the primary outputs. Additionally or alternatively, timing in the circuit may be analyzed to determine a bound of timing delay of the circuit for one or more parameter corners in a parameter space and if the bound of timing delay is worse than a threshold time delay then one or more parameter corners may be pruned from the parameter space using branch and bound techniques.

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Lisboa, Portugal

Luis Guerra E Silva