Intel Corporation

Luis Giles

Peter Baumgartner

Marko Radosavljevic

Han Wui Then

Sansaptak W Dasgupta

Harald Gossner

Franz Kuttner

Christian Cornelius Russ

Philipp Riess

Uwe Hodel

Richard Geiger

Georgios Panagopoulos

Bernhard Stein

Andreas Lachmann

Vase Jovanov

Gregor Bracher

Karl-Henrik Ryden

Giuseppe Curello

Tomasz Biedrzycki

Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

III-N diodes with n-doped wells and capping layers

A semiconductor device is proposed. The semiconductor device includes a source region of a field effect transistor having a first conductivity type, a body region of the field effect transistor having a second conductivity type, and a drain region of the field effect transistor having the first conductivity type. The source region, the drain region, and the body region are located in a semiconductor substrate of the semiconductor device and the body region is located between the source region and the drain region. The drain region extends from the body region through a buried portion of the drain region to a drain contact portion of the drain region located at a surface of the semiconductor substrate, the buried portion of the drain region is located beneath a spacer doping region, and the spacer doping region is located within the semiconductor substrate.

Semiconductor devices and methods for forming semiconductor devices

Described is an apparatus which comprises: a pad; a first transistor coupled in series with a second transistor and coupled to the pad; and a self-biasing circuit to bias the first transistor such that the first transistor is to be weakly biased during an electrostatic discharge (ESD) event. Described is also an apparatus which comprises: a first transistor; and a first local ballast resistor formed of a trench contact (TCN) layer, the first local ballast resistor having a first terminal coupled to either the drain or source terminal of the first transistor.

Area-efficient and robust electrostatic discharge circuit

Growing community of inventors

Neubiberg, Germany

Luis Giles