Qualcomm Incorporated

Luis Chen

Jeffrey Mark Hinrichs

Kevin Jia-Nong Wang

Thomas Hua-Min Williams

Keyurkumar Karsanbhai Kansagra

Smeeta Heggond

Matthew Chauncey Kusbit

Certain aspects of the present disclosure provide methods and apparatus for minimizing, or at least reducing, a bias noise contribution to phase noise in an oscillator circuit. One example oscillator circuit generally includes an oscillator configured to generate an oscillating signal, an adjustable bias circuit coupled to a bias input of the oscillator and configured to provide a bias signal to the oscillator, and a control circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable bias circuit. The control circuit is configured to control the adjustable bias circuit to adjust the bias signal with a control signal, to determine an impact of the adjusted bias signal on a parameter of the oscillating signal, and to determine a setting for the control signal based on the impact on the parameter of the oscillating signal.

Phase noise reduction by controlling biasing for adjustable oscillators with cross-coupled transistors

An apparatus, including: a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer includes a first buffer stage including: a first field effect transistor (FET); a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail; a third FET; a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal; and a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs.

Buffer for voltage controlled oscillator (VCO) or other applications

An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.

Comb / fishbone metal stack

A bias circuit is provided that is configure to control the bias for a diode-connected transistor operating in the sub-threshold region to produce a gate-to-source voltage. A differential tuning voltage derived from the gate-to-source voltage tunes a plurality of varactors.

Bias circuit for temperature-compensated varactor

Oscillator circuits and methods are disclosed. In an embodiment, a circuit includes a voltage controlled oscillator (VCO) and a regulator coupled to a supply input of the VCO. The circuit also includes an oscillation dampening circuit coupled to an output of the regulator. A resistance or a capacitance of the oscillation dampening circuit is configured to vary based on current provided to the VCO.

Growing community of inventors

Chula Vista, CA, United States of America

Luis Chen