International Business Machines Corporation

Luis A Lastras

Michele M Franceschini

Peter Anthony Franaszek

John Peter Karidis

Ashish Jagmohan

Moinuddin K Qureshi

Bulent Abali

Patrick James Meaney

Kyu-hyoun Kim

Hillery C Hunter

Charles Arthur Kilmer

Eldee Stephens

George C Wellwood

Chung H Lam

Vittorio R Castelli

Hubertus Franke

Bipin Rajendran

Mohammad Banikazemi

Dan Edward Poff

Mayank Sharma

Stefanie Ruth Chiras

A compression engine and method for optimizing the high compression of a content addressable memory (CAM) and the efficiency of a static random access memory (SRAM) by synchronizing a CAM with a relatively small near history buffer and an SRAM with a larger far history buffer. An input stream is processed in parallel through the near history and far history components and an encoder selects for the compressed output the longest matching strings from matching strings provided by each of the near history and far history components. A further optimization is enabled by selectively disabling one or the other of the two types of compressors.

Hybrid compression for large history compressors

An aspect of this invention is a method for providing a PreSET region in a memory device wherein the PreSET region includes one or more lines of the memory device which have been PreSET; performing a write operation on one or more out of place lines of the memory device by writing to the PreSET region instead of writing to an in place line of the memory device; and storing in an indirection table a mapping of each of a respective plurality of logical pages of the memory device to a corresponding physical page of a plurality of physical pages of the memory device, wherein the indirection table keeps track of the one or more out of place lines.

Out-of-place presetting based on indirection table

Techniques are presented that include determining, for data to be written to a nonvolatile memory, a location in the nonvolatile memory to which the data should be written based at least on one or more wear metrics corresponding to the location. The one or more wear metrics are based on measurements of the location. The measurements estimate physical wear of the location. The techniques further include writing the data to the determined location in the nonvolatile memory. The techniques may be performed by methods, apparatus (e.g., a memory controller), and computer program products.

Variability aware wear leveling

A compression engine and method for optimizing the high compression of a content addressable memory (CAM) and the efficiency of a static random access memory (SRAM) by synchronizing a CAM with a relatively small near history buffer and an SRAM with a larger far history buffer. An input stream is processed in parallel through the near history and far history components and an encoder selects for the compressed output the longest matching strings from matching strings provided by each of the near history and far history components.

Embodiments relate to stale data detection in a marked channel for a scrub. An aspect includes bringing the marked channel online, wherein the computer comprises a plurality of memory channels comprising the marked channel and a remaining plurality of unmarked channels. Another aspect includes performing a scrub read of an address in the plurality of memory channels. Another aspect includes determining whether data returned by the scrub read from the marked channel is valid or stale based on data returned from the unmarked channels by the scrub read. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is valid, not performing a scrub writeback to the marked channel. Another aspect includes based on determining that the data returned by the scrub read from the marked channel is stale, performing a scrub writeback of corrected data to the marked channel.

Stale data detection in marked channel for scrub

A method for detecting memory cells that are stuck in a physical state. The method includes performing a diagnostic read of a memory cell in a memory system. The memory system is configured to utilize at least one read threshold value to determine a read data value stored in the memory cell when performing a data read operation on the memory cell. Performing the diagnostic read includes: comparing a measurement property of the memory cell to at least one diagnostic threshold value, where at least one of the diagnostic threshold values is different from all of the read threshold values; and identifying the memory cell as being stuck in a physical state based on the comparing. Based on identifying the memory cell as being stuck in a physical state, an indication that memory cell is stuck is output along with a diagnostic data value associated with the physical state.

Detection of memory cells that are stuck in a physical state

A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh.

DRAM refresh

A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set.

Method for optimizing refresh rate for DRAM

Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.

Writing to memory using shared address buses

Techniques for writing to memory using adaptive write techniques. An adaptive write technique includes receiving at a computer a message including a plurality of symbols. The message is written to a memory. The writing to memory includes performing for each symbol in the message: writing a data value to a memory location in the memory and reading contents of the memory location after the data value has been written. The data value is determined at the computer in response to the symbol and to the contents of any memory locations previously read as part of writing the message to the memory. It is determined at the computer if the contents of the memory locations reflect the message. The writing is restarted at the computer in response to determining that the contents of the memory locations do not reflect the message.

Writing to memory using adaptive write techniques

Techniques for reading phase change memory that mitigate resistance drift. One contemplated method includes apply a plurality of electrical input signals to the memory cell. The method includes measuring a plurality of electrical output signals from the memory cell resulting from the plurality of electrical input signals. The method includes calculating an invariant component of the plurality of electrical output signals dependent on the configuration of amorphous material in the memory cell. The method also includes determining a memory state of the memory cell based on the invariant component. In one embodiment of the invention, the method further includes mapping the plurality of electrical output signals to a measurements region of a plurality of measurements regions. The measurements regions correspond to memory states of the memory cell.

Memory reading method for resistance drift mitigation

The present invention describes lossless data compression/decompression methods and systems. A random access memory (RAM) operates as a static dictionary and includes commonly used strings/symbols/phrases/words. An input buffer operates as a dynamic dictionary and includes input strings/phrases/symbols/words. A set-associative cache memory operates as a hash table, and includes pointers pointing to the commonly used strings/symbols/phrases/words in the static dictionary and/or pointing to one or more of the input strings/phrases/symbols/words in the dynamic dictionary. Alternatively, the set-associative cache memory combines the dynamic dictionary, the static dictionary and the hash table. When encountering a symbol/phrase/string/word in the static or dynamic dictionary in an input stream, a compressor logic or module places a pointer pointing to the symbol/phrase/string/word at a current location on the output stream. The hash table may include phrases/symbols/strings/words and/or pointers pointing to phrases/symbols/strings/words.

Data compression using a nested hierachy of fixed phrase length static and dynamic dictionaries

A content addressable memory using encoded data words and search words, and techniques for operating such device. In one embodiment, the data word is transformed into a code word guaranteeing a mismatch of at least two code word bits of different binary values during the memory search operation when the data word does not match a search word. In another embodiment, the search word is transformed into a search code such that the Hamming distance between the code word and the search code is greater than a given threshold when there is a mismatch of at least one bit between the data word and the search word.

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Cortlandt Manor, NY, United States of America

Luis A Lastras