Motorola Corporation

Luis A Bonet

David Yatim

Jose G Corleto

James Ward Girardeau, Jr

Michael Dale Floyd

Alan Lee Westwick

Tim A Williams

Carlos A Greaves

Brian T Kelley

Mauricio A Zavaleta

Nicole D Teitler

Steven E Cozart

David E Bush

James Alan Tuvell

A mixer (,) including a transformation circuit (,) is used for frequency converting a first digital signal (,), sampled at a first sampling rate and operating at a first frequency, to a second digital signal (,) operating at a desired frequency. The transformation circuit (,) is adapted to modify and filter the first digital signal (,) to eliminate unwanted frequencies in the first digital signal (,) and to alter the first sampling rate of the first digital signal (,) by a predetermined factor to generate a modified and filtered first digital signal (,) operating at a second sampling rate and the first frequency. The transformation circuit (,) is further adapted to mix the modified and filtered first digital signal (,) with a predetermined injection signal (,) to generate the second digital signal (,) operating at the desired frequency and the second sampling rate.

Method and apparatus for mixing signals

A mixed signal processing system (22) includes digital (28) and analog (29) systems and is powered by a variable external voltage, such as a battery voltage. A voltage regulator (41) regulates the battery voltage to a nominal potential less than the battery voltage. The voltage regulator (41) provides the regulated voltage to a digital subsystem (51) of the digital system (28). A regulated charge pump (43) provides a voltage which is above the battery voltage and substantially constant due to regulation. The regulated charge pump (43) provides the regulated charge-pumped voltage to an analog subsystem (61) of the analog system (29) for better analog operation. A level shifter (44) equalizes signal levels between the digital (28) and analog (29) systems.

Mixed signal processing system and method for powering same

A digital signal processor (10) includes a primary data bus (12), a primary instruction bus (14), a program control unit (16), an arithmetic unit (18), and a multiplier (20). Within the program control unit (16), multi-instruction words are issued from program memory (22) to the primary instruction bus (14). These multi-instruction words allow both logical and arithmetic instructions to be performed simultaneously. The arithmetic unit (18) includes a secondary data bus (44) which couples the arithmetic unit to the accumulator (34). The arithmetic unit (18) also includes a barrel shifter (48) having sign extension to reduce the number of operations required to shift data. The arithmetic logic unit (32) further includes complex arithmetic functions resulting in fewer operations per instruction and a multiplier (50) which is used for filtering operations in digital filtering and by the arithmetic unit (18).

Digital signal processor for executing multiple instruction words

Read Only Memory (ROM) (10) data may be selectively inverted to decrease energy dissipation. Within the ROM (10), a plurality of memory cells (16) are connected to bit-line (18) and word-line (20) and store data, which determines the loading for a particular line. Line loading may be manipulated by accessing initial mapping information (23) of the ROM (10) and calculating the line loading on each line (18 or 20) and whenever a line's load exceeds a threshold, data stored in the memory cells (16) on the particular line (18 or 20) are inverted. Having done this, new mapping information (23) is produced and used to retrieve data from the ROM (10).

ROM mapping and inversion apparatus and method

A digital cordless telephone (10) includes a handset (12) and a base station (14). A voice activity detector (20) in the handset (12) determines whether speech or silence is being received by a microphone (13) in the handset (12). An active enable signal is transmitted to the base station (14) when silence is being transmitted. An adaptive comfort noise generator (30) in the base station (14) then provides a comfort noise to a destination telephone instead of the silence. The output level of the comfort noise is a function of an energy level of a linear data signal received by the base station (14) before the enable signal becomes active.

Method and apparatus for reducing power consumption in a communications

Method and apparatus of an enhanced digital signal processor

An ADPCM transcoder (60) includes an integral tone generator (65) which inserts a linear tone signal, such as a conventional DTMF tone signal, into either the transmit or receive data stream, or both. A digital PCM input signal is first converted to a first linear signal. If tone generation is enabled for transmission, then the linear tone signal is substituted for or added to the first linear signal and provided to an ADPCM encoder (63), which provides an ADPCM output signal in response. An ADPCM decoder (66) receives an ADPCM input signal and provides a second linear input signal in response. If tone generation is enabled for reception, then the linear tone signal is substituted for or added to the second linear input signal, and converted to a digital PCM output signal. The ADPCM transcoder (60) may also be integrated with other components of a signal processing system.

ADPCM transcoder with integral tone generation and method therefor

A signal processor such as an ADPCM decoder (28b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, ADPCM decoder (28b) processes the input signal to provide a linear reconstructed signal s.sub.r (k). When enabled, a noise detector (50) samples the reconstructed signal s.sub.r (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of the reconstructed signal s.sub.r (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. This calculation prevents the need for time-consuming division operation which is difficult for high-performance digital signal processors (70).

Method and apparatus for noise burst detection in a signal processor

A signal processor such as an ADPCM decoder (128b) receives an input signal. As part of the CCITT Recommendation G.726 algorithm, an inverse adaptive quantizer (41) processes the input signal to provide a quantized difference signal d.sub.q (k). When enabled, a noise detector (50) samples signal d.sub.q (k) once for each of a predetermined number of received samples. The noise detector (50) adds the absolute value of signal d.sub.q (k) to a total energy estimate. At the end of the predetermined number of samples, the noise detector (50) compares the total energy estimate to a product of a noise threshold and the predetermined number. If the total energy estimate exceeds this product, then a noise indication is provided. In another embodiment (228b) a noise detector (250) compares an existing energy estimate signal d.sub.ml (k) computed by an adaptation speed control block (48) as part of the G.726 algorithm to an energy threshold to save processing time.

An integral digital receive gain (44) for a G.721 or G.726 ADPCM decoder (28a) or the like in an application such as a CT-2 handset (20) allows digital volume control without the need for external components. The digital receive gain (44) receives a reconstructed signal s.sub.r (k) and a variable gain factor. The integral digital receive gain (44) multiplies the reconstructed signal by the gain factor and provides the result as an input to an output PCM format conversion (45). The digital receive gain (44) also disables a synchronous coding adjustment (46) if a gain setting other than unity gain is detected.

ADPCM decoder with an integral digital receive gain and method therefor

A data processor having a split level control store structure, which partitions program memory into a macrocode portion and a microcode portion. The data processor contains two distinct machines, a macromachine and a micromachine. The macromachine includes an instruction sequence controller which detects the macrocode branch instruction before it is perceived by the micromachine, extracts from the branch instruction a macroaddress, and then provides the extracted macroaddress to the program memory as the next sequential instruction address. By 'pipelining' the macromachine, the macromachine can 'execute' the branch instruction in parallel with, and independent of, the execution by the micromachine of the preceeding instruction.

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Austin, TX, United States of America

Luis A Bonet