Globalfoundries Inc.

Globalfoundries U.S. Inc.

Luigi Pantisano

Jagar Singh

Shahab Siddiqui

Srikanth Balaji Samavedam

Frank Scott Johnson

Anil Kumar

Anvitha Shampur

Abu Naser M Zainuddin

Beth Baumert

Premachandran Chirayarikathuveedu

Rakesh Ranjan

A semiconductor device is disclosed including a semiconductor layer, a first well doped with dopants of a first conductivity type defined in the semiconductor layer, a second well doped with dopants of a second conductivity type different than the first conductivity type defined in the semiconductor layer adjacent the first well to define a PN junction between the first and second wells, and an isolation structure positioned in the second well. The semiconductor device also includes a first source/drain region positioned in the first well, a second source/drain region positioned in the second well adjacent a first side of the isolation structure, a doped region positioned in the second well adjacent a second side of the isolation structure, and a gate structure positioned above the semiconductor layer, wherein the gate structure vertically overlaps a portion of the doped region.

Semiconductor device with doped region adjacent isolation structure in extension region

At least one method, apparatus and system are provided for forming a hybrid oxide layer for providing for a first region of a finFET device to operate at a first voltage and a second region of the finFET to operate at a second voltage. A first set of fins are formed on an I/O device portion, and a second set of fins are formed on a core device portion of a substrate. A first and a second oxide layers are deposited on the first and second set of fins, wherein they merge to form a hybrid oxide layer. The thickness of the second oxide layer is based on a first operating voltage for the I/O device portion. The hybrid layer is removed from the core device portion such that the I/O device portion operates at the first voltage and the core device portion operates at a second voltage.

Methods, apparatus and system for forming a FinFET device comprising a first portion capable of operating at a first voltage and a second portion capable of operating at a second voltage

A device and method to control the heating of an IC chip in a wafer form for measuring various parameters associated therewith are provided. Embodiments include a device having a silicon layer with an upper surface, and on a plastic carrier; a plurality of devices in the silicon layer and electrically coupled through the upper surface to a test control system; a through silicon via (TSV) extending into the silicon layer; and a parallel heating structure adjacent to the plurality of devices electrically coupled to the test control system.

Method and apparatus for quantifying defects due to through silicon VIAs in integrated circuits

Growing community of inventors

Saratoga Springs, NY, United States of America

Luigi Pantisano