Cselt-centro Studi E Laboratori Telecomunicazioni S.p.a.

Cselt- Centro Studi E Laboratori Telecommunicazioni Spa

Presidenza Dei Consiglio Dei Ministri Del Ministro Per Il Coordinamento

Luigi Licciardi

Maura Turolla

Alessandro Torielli

Vinicio Vercellone

Marco Gandini

Luciano Pilati

Alberto Ciaramella

Giovanni Venuti

Robert Tasso

Riccardo Cecinati

Maurizio Paolini

The capacity of switching elements, for instance 8.times.8 elements, is expanded, to originate single-stage elements with greater capacity (16.times.16 or 32.times.32), by arranging an even plurality of such elements in an output substage and by placing upstream of the output substage at least a first input substage comprising a corresponding even plurality of the switching elements. The even and, respectively, the odd outputs of the elements of the input substage are connected in an orderly manner to the inputs of the switching elements of the output substage. A routing management logic to obtain single-stage elements is also provided within each individual switching element.

Method of expanding the capacity of switching elements, and switching

The switching element allows building up of ATM exchanges capable of processing cell flows at bit rates higher than 700 Mbit/s. It uses an architecture with output queues, implemented through a unique shared memory, suitably controlled in order to obtain spatial cell switching towards the outputs. ATM cells are converted into a highly parallel format by a structure named rotation memory, where through the cells are then transferred into the master memory. The rotation memory is used also for the inverse operations of format restoration towards the output. The element control circuit is entrusted with the generation of writing and reading addresses of the master memory, in order to carry out the switching proper.

High bit rate cell switching element in CMOS technology

This connected-speech recognition system uses a two-level hierarchical system, in which the higher-level (master) processor and one or more lower-level units (slaves) process, respectively, the most probably word sequence within a permitted grammar network, and the likelihood of individual words with the grammar network. The lower-level processing performs dynamic programming involving vector and matrix calculation and comparison, and processing speed is improved by an integrated processing unit which has simultaneous access to the external data memory as well as to a high-speed internal microinstruction ROM. One of the aforementioned units can also provide for performing an additional internal test function. The structure features two internal data buses and internal memories for more commonly used data and addresses, for enabling high-speed microinstruction performance and external memory access. The external memory is divided into tables differing structurally but such as to be accessed in uniform manner by the internal addressing unit.

Integrated processing unit, particularly for connected speech

The elementary adder, as far as carry propagation is concerned, has two circuit branches: the first is an inverter (II) followed by a transfer gate (T1, T2) activated when two operands have opposite logic levels, in which case it transfers complemented input carry Cin to the output CoutN; the second consists of a 4-transistor series cirucit, two P-MOS (T3, T4) and two N-MOS (T5, T6) geenrating carry output CoutN complemented when the two operands have equal logic levels.

CMOS cell for logic operations with fast carry

The arithmetic-logic unit has elementary cells performing logic addition, one for each pair of operand bits, which are particularly optimized as far as carry propogation speed is concerned and are controlled by an auxiliary fast logic allowing their performance to be extended to the other operations. The unit also has a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell.

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Almese, Italy

Luigi Licciardi