Texas Instruments Corporation

University of Texas System

Other

Drs Network & Imaging Systems, LLC

Tokyo Electron Limited

Raytheon Company

Agilent Technologies, Inc.

Agilent Technologies Texas Instruments Incorporated

Luigi Colombo

Mark R Visokay

Archana Venugopal

James Joseph Chambers

Antonio L P Rotondaro

Benjamin Stassen Cook

Scott Robert Summerfelt

Robert R Doering

Nazila Dadvand

Theodore Sidney Moise

Stephen Roy Gilbert

Antonio Luis Pacheco Rotondaro

Haowen Bu

Guoqiang Xing

Poornika Fernandes

Sanjeev Aggarwal

Marie Denison

Francis Gabriel Celii

Arup Polley

Malcolm John Bevan

Justin F Gaynor

Douglas E Mercer

James Cooper Wainerdi

Rodney S Ruoff

Hiroaki Niimi

Rajesh B Khamankar

Sameer P Pendharkar

Robert M Wallace

Darvin R Edwards

Paul C McIntyre

Manuel A Quevedo-Lopez

Hiep Xuan Nguyen

Robert William Murto

Tim Svoboda

Victor Perez-Rubio

Lance Robertson

Kathryn O'Brien

Fred Raymel Harris

J Scott Martin

Laura Wills Mirkarimi

Tatsuo Matsudo

Shawming Ma

Sanjay K Banerjee

Kelly Jay Taylor

Lindsey H Hall

Husam N Alshareef

John Paul Tellkamp

Jun Amano

Takuya Sugawara

Donald F Weirauch

Emanuel Tutuc

John Paul Campbell

Trace Quentin Hurd

Sebastian R Borrello

K R Udayakumar

Tomoyuki Sakoda

Mark A Kressley

Herbert F Schaake

Carlos A Castro

Rahim Kavari

Seyoung Kim

Koji Shimomura

Yufeng Hao

Sirisha Kuchimanchi

Alvin L S Loke

Laura Wills-Mirkarimi

Sagnik Dey

Xuesong Li

Kent R Carson

A system for growing a CdZnTe crystal includes a crucible operable to contain a solid CdZnTe source and a heating element operable to melt an upper surface to the solid CdZnTe source and form a tellurium rich melt floating on the solid CdZnTe source. The crucible is operable to contain an encapsulating layer above the tellurium rich melt. The system also includes a rod operable to mechanically support a CdZnTe seed crystal.

Method and system for liquid encapsulated growth of cadmium zinc telluride crystals

A method of forming a composite material includes photo-initiating a polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice. Unpolymerized monomer is removed from the polymer microlattice. The polymer microlattice is coated with a metal. The metal-coated polymer microlattice is dispersed in a polymer matrix.

Filler particles for polymers

An integrated circuit has a substrate that includes a semiconductor material, and an interconnect region disposed on the substrate. The integrated circuit includes a thermal routing trench in the substrate. The thermal routing trench includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal routing trench has a thermal conductivity higher than the semiconductor material contacting the thermal routing trench. The cohered nanoparticle film is formed by an additive process.

Thermal routing trench by additive processing

A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

-bonded carbon structures

A method of growing a cadmium zinc telluride (CdZnTe) crystal includes providing a crucible including a solid CdZnTe source and forming a Te-rich Cd—Zn—Te melt on the solid CdZnTe source. The method also includes positioning a CdZnTe seed crystal in physical contact with the Te-rich Cd—Zn—Te melt and growing the CdZnTe crystal from the Te-rich Cd—Zn—Te melt.

An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

IC with 3D metal-insulator-metal capacitor

An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

High thermal conductivity vias by additive processing

In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V; and a capacitor second plate over the dielectric stack.

Precision capacitor

In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice. A ceramic may be deposited on the graphene and another graphene layer may be deposited on top of the ceramic to create a multi-layered sp-bonded carbon tube.

Multi-layered SP-bonded carbon tubes

A microstructure comprises a plurality of interconnected units wherein the units are formed of hexagonal boron nitride (h-BN) tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing an h-BN precursor on the metal microlattice, converting the h-BN precursor to h-BN, and removing the metal microlattice.

Hexagonal boron nitride structures

A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.

Multi-super lattice for switchable arrays

A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

Integration of graphene and boron nitride hetero-structure device over semiconductor layer

A composite material comprises a polymer matrix having microstructure filler materials that comprise a plurality of interconnected units wherein the units are formed of connected tubes. The tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, growing or depositing a material on the metal microlattice such as graphene, hexagonal boron nitride or other ceramic, and subsequently removing the metal microlattice.

An interconnect structure for a semiconductor device includes a plurality of unit cells. Each unit cell is formed of interconnected conducting segments. The plurality of unit cells forms a conducting lattice.

Lattice bump interconnect

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Dallas, TX, United States of America

Luigi Colombo