Advanced Micro Devices Corporation

Globalfoundries Inc.

Other

Advanced Micro Technologies, Inc.

Luigi Capodieci

Todd P Lukanc

Christopher A Spence

Carl P Babcock

Cyrus E Tabery

Hung-Eil Kim

Vito Dai

Chris Haidinyak

Lynn Wang

Bhanwar Singh

Sarah McGowan

Joerg Reiss

Ramkumar Subramanian

Scott Allan Bell

Marina V Plat

Jie Yang

Yi Zou

Sriram Madhavan

Swamy Muddu

Amit P Marathe

Anna Maria Minvielle

Piyush Pathak

Rani Abou Ghaida

Ahmed Mohyeldin

Norma Rodriguez

Abde Ali Kagalwalla

Swamy Maddu

Lodewijk Hubertus Van Os

Peng Xie

Juan Andres Torres Robles

A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include scanning a drawn semiconductor design layout to determine a difficult-to-manufacture pattern within the drawn semiconductor design layout based on a match with a pre-characterized difficult-to-manufacture pattern, determining a corrected pattern based on a pre-determined correlation between the corrected pattern and the pre-characterized difficult-to-manufacture pattern, and replacing the difficult-to-manufacture pattern with the corrected pattern within the drawn semiconductor design layout.

Automated design layout pattern correction based on context-aware patterns

Methodology enabling a reduction in a density difference between two complementary exposure masks and/or windows of a layout and an apparatus for performing the method are disclosed. Embodiments include: determining a layer of an IC design having features to be resolved by first and second masks; determining a difference of density by comparing a first density of a first set of the features with a second density of a second set of the features; determining a region on the layer of a first feature to be resolved by the first mask; and inserting, within the region, a polygon to be resolved by the second mask based on the difference of density.

Stitch insertion for reducing color density differences in double patterning technology (DPT)

One illustrative method disclosed herein involves producing an initial circuit layout, prior to decomposing the initial circuit layout, identifying at least one potential non-double-patterning-compliant (NDPC) pattern in the initial circuit layout, fixing the at least one potential non-double-patterning-compliant (NDPC) pattern so as to produce a double-patterning-compliant (DPT) pattern, producing a modified circuit layout by removing the potential non-double-patterning-compliant (NDPC) pattern and adding the double-patterning-compliant (DPT) pattern to the initial circuit layout, and performing design rule checking and double patterning compliance checking on the modified circuit layout.

Methods involving pattern matching to identify and resolve potential non-double-patterning-compliant patterns in double patterning applications

A process and apparatus are provided for automated pattern-based semiconductor design layout correction. Embodiments include: determining a portion of a layout of an IC design, the portion comprising a first pattern of a plurality of routes connecting a plurality of design connections; determining one or more sets of the plurality of design connections based on the plurality of routes; and determining, by a processor, a second pattern of a plurality of routes connecting the plurality of design connections within the portion based on the one or more sets.

Layout pattern correction for integrated circuits

Methods and apparatus are provided for analyzing impact of design rules on a layout. One exemplary method involves generating variants of the layout for different values for the rule, determining values of a device metric for each of the layout variants, and identifying the relationship between rule and the device metric based on the values for the device metric corresponding to the different values for the rule. In one embodiment, the layout variants are generated by using the different values for the rule to perform layout compaction on an initial layout generated in accordance with an initial value for the rule.

Methods for analyzing design rules

Methods for fabricating semiconductor devices are provided. In an embodiment, a method of fabricating a semiconductor device includes scanning a circuit design layout and proposing patterns for decomposed layouts. The proposed patterns are then compared with a library of prior patterns including a category of forbidden patterns and a category of preferred patterns. If a selected proposed pattern matches a forbidden pattern, the selected proposed pattern is eliminated. If the selected proposed pattern matches a preferred pattern, then the selected proposed pattern is identified for use in the decomposed layouts. Decomposed layouts are generated from the identified patterns. A plurality of masks is fabricated based on the decomposed layouts. Then a multiple patterning lithographic technique is performed with the plurality of masks on a semiconductor substrate.

Methods for decomposing circuit design layouts and for fabricating semiconductor devices using decomposed patterns

A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a double patterning technology-compliant logical design for the integrated circuit, the logical design including a plurality of elements; scoring the design of one or more of the plurality of elements to produce a design score; modifying the design based at least in part on the design score; generating a mask set implementing the modified logical design; and employing the mask set to implement the logical design in and on a semiconductor substrate.

Methods for quantitatively evaluating the quality of double patterning technology-compliant layouts

A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing a drawn layout logical design for the integrated circuit, the logical design including a plurality of patterns; checking the plurality of patterns for double patterning technology compliance; identifying a non-double patterning technology compliant pattern; providing a double patterning technology compliant pattern for replacing the identified non-double patterning technology compliant pattern, thereby creating a modified logical design; generating a mask set implementing the modified logical design; and employing the mask set to implement the modified logical design in and on a semiconductor substrate.

Methods for pattern matching in a double patterning technology-compliant physical design flow

A method of correcting a lithographic mask is disclosed. The method can include detecting a location of the mask that corresponds to a wafer location having a structure that is printed with a larger than desired dimension and reducing a thickness of at least a portion of a mask feature corresponding to the wafer structure to locally increase transmissivity of the mask feature.

Method of lithographic mask correction using localized transmission adjustment

An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns, and inverse lithography is performed on the unique feature layouts to form assist features. The resulting layout of assist features is analyzed to create an assist feature rules set. The rules can then be applied to a photomask patterned with the integrated circuit design layout to print optimal assist features. The resulting photomask may be used to form an integrated circuit on a semiconductor substrate.

System for generating and optimizing mask assist features based on hybrid (model and rules) methodology

A method of forming a feature on a device is disclosed. A photo resist layer is formed over the device and a dipole illuminator having a pole orientation axis in a first direction is used to expose a first geometrical pattern onto the resist layer. The first geometrical pattern is substantially oriented in the same direction as the pole orientation axis of the dipole illuminator. A dipole illuminator having a pole orientation axis substantially orthogonal to the first direction then is used to expose a second geometrical pattern onto the resist layer. The second geometrical pattern is oriented substantially orthogonal to the first direction.

Single/double dipole mask for contact holes

Layout patterns are identified as problematic when they have particular parameters required to exceed standard limits. The problematic layout patterns are associated with preferred design rules in a DRC-Plus deck. Layout data is scanned to generate match locations of any problematic layout patterns. The match locations are forwarded to a DRC engine that compares layout parameters of the match locations to corresponding preferred layout rules in the DRC-Plus deck. The DRC-Plus check results are used to modify the layout to improve manufacturability of the layout.

Design rules checking augmented with pattern matching

A method of selecting a plurality of lithography process parameters for patterning a layout on a wafer includes simulating how the layout will print on the wafer for a plurality of resolution enhancement techniques (RETs), where each RET corresponds to a plurality of lithography process parameters. For each RET, the edges of structures within the simulated layout can be classified based on manufacturability. RETs that provide optimal manufacturability can be selected. In this manner, the simulation tool can be used to determine the optimal combination of scanner setup and reticle type for minimizing the variation in wafer critical dimension (CD).

System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques

A method includes providing an initial IC device design, which design has a desired set of electrical characteristics. A layout representation corresponding to the initial device design is generated. A simulation tool is used to determine whether the layout representation corresponds to an IC device design having the desired electrical characteristics. In addition, the variation between structures within IC device designed due to process variations is evaluated using the simulation tool. This variation can be used to determine whether the design is optimized.

System and method for designing an integrated circuit device

A chromeless phase-shift mask (CPM) for imaging sub-100 nm contact holes and a method of making the same are disclosed. The CPM includes a plurality of features formed on a substrate and a plurality of suppressors formed on the substrate. Light energy passing through the plurality of suppressors substantially reduces an interference generated by light energy passing through features within an optical proximity of each other, thereby significantly improving contrast and depth of focus. The plurality of features can be formed in a grid pattern, and the suppressors can be formed in adjacent corners of each feature. The size and location of the suppressors can be varied with respect to the features to obtain a desired image.

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Santa Cruz, CA, United States of America

Luigi Capodieci