Ampex Corporation

Accom

Luigi C Gallo

John D Stern

Douglas J George

Daniel A Beaulier

Kenneth Louth

Sohei Takemoto

Jerry W Miller

Kenneth A Woodhouse

Junaid Sheikh

Jose Alvarez

Sohei Takamoto

In a component video signal to composite video signal encoding system (10), the component input signals are stored in a first in, first out (FIFO) memory. The FIFO memory is connected by 1 luminance and 2 chrominance outputs to a rate converter, which increases the digital sampling rate of the signals as received from the FIFO memory. The rate converter is in turn connected by 1 luminance and 2 chrominance outputs to luminance and chrominance processing circuits. The luminance and chrominance processing circuits produce the composite video signals, and are connected to a D2 standard driver circuit. The output of the D2 driver circuit is D2 standard digital component signals. The luminance and chrominance processing circuits are also connected to a digital to analog (D/A) converter. The output of the D/A converter is an analog or NTSC component video signal.

Component video signal to composite video signal encoding system,

A digital still store system (10) receives composite digital 4:2:2 D1 video signal inputs in parallel at (12) or serially at (14). The signals are supplied in component form selectively to one of framestores (18) and (20). The component signals are supplied from the framestores (18) and (20) to hard disks (22) through a buffer store (24) and disk input/output (I/O) circuits (26). Each of the hard disks (22) stores still video images as either 525 or 625 line digital frames for either NTSC or composite signal inputs and outputs. Y and C fields of component video signal information are supplied from the hard disks (22) through the buffer store (24) and one of the frame stores 18 and 20 to a compositor (28) for output as digital 4:2:2 video signals. The buffer store (24) obtains the video signal fields for either full size images or 1/4 size images, when an array for browsing and selection is desired. When the 1/4 size images are desired, the field video signals are obtained by addressing every fourth pixel of the field for readout.

Still store system and method with simple image access

According to a presently preferred embodiment of the invention, image enhancement apparatus for digital video images comprises a two-stage filter comprising a median filter and a recursive filter. The median filter operates in one, two, and three dimensions wherein the cluster of pixels framing the center pixel are ranked, and the median value of the pixel cluster is chosen as the correct pixel value. The pixel cluster configuration is selectable, as are the planes where the pixels are located. Multiple weights may be given to the appropriate median filter inputs. A motion detector is used to prevent replacement of each pixel by its pixel cluster median value when there is excessive motion. Finally an adjustable pixel-replacement threshold is defined. Each pixel must deviate from its median value before it is replaced by that value. In the presence of rapid motion in the picture, the operation of the median filter is reduced or halted by a properly derived motion signal according to the present invention, thus preventing motion artifacts from occurring.

Three-dimensional median and recursive filtering apparatus and method

A real-time disk system (10) stores and plays back D1 digital 10-bit 4:2:2 component video and audio signals from magnetic storage disks (12). The system (10) has a main channel subsystem (14) with an associated smooth motion option (16) and a second or key channel option subsystem (18) with an associated smooth motion option (20). Serial and parallel D1 digital video inputs (30) and (32) and outputs (34) and (36) are connected to each of the channels (14) and (18) and to control subsystem (22). In the main channel (14), the serial and parallel D1 input (30) is connected through an input board (60) to a video processing board (62). The video board (62) is connected by a bidirectional, 11.times.2 wide bus (64) to disk arrays (66) and (68). Digital video signal information is stored and retrieved in parallel to and from the disk arrays (66) and (68) without requiring any serial to parallel or parallel to serial conversion. Smooth motion option (20) processes a group of video fields by creating a plurality of additional fields between two original fields in the group of video fields by a combination of motion adaptive interpolation and frame repetition.

Real-time disk system

A decoding system (10) receives a composite digital NTSC D2 input signal or a composite analog NTSC RS-170A input signal. The decoding system (10) decodes and sample rate converts to a component digital D1 output and a component analog RGB or Y(R-Y) (B-Y) output. A control panel (20) is connected to the decoding system (10) to provide digital control of the important decoding parameters to provide decoding flexibility. The composite video signal is supplied directly to an adaptive combiner (44), through a line comb filter (48) to the adaptive combiner (44), and through a frame comb filter (52) to the adaptive combiner (44). The composite video signal is also supplied to a frame transition or motion detector (58) and to a line transition or motion detector (60). If no frame transition or motion is detected, the adaptive combiner (44) utilizes frame based three dimensional decoding. When frame transition or motion is detected, the adaptive combiner (44) drops back to two dimensional line combing for the decoding. When line transition or motion is detected, the adaptive combiner drops back to supply the video signal directly to band pass filter (62) for bandpass decoding. Thus, for those parts of a scene in which there is motion or vertical detail, the decoding system 10 automatically adapts to line combing or bandpass decoding smoothly within the scene to give high apparent resolution in the scene.

Three dimensional adaptive decoding system and method

An analog color video information signal is sampled at times determined by a first clock signal of a predetermined frequency whose phase is reversed on every consecutive horizontal line. The obtained samples are digitized and encoded for recording on a magnetic record medium, with the encoded data timed relative to a second clock signal of the predetermined frequency whose phase is continuous. The reproduced encoded data is processed under the control of two additional clock signals, each of which is of the predetermined frequency and has its phase reversed on every consecutive horizontal line. In the processing, the reproduced data is decoded, reclocked relative to a first of the two additional clock signals, has the chrominance component of the video information selectively inverted and converted back to analog form under the control of the second of the two additional clock signals.

Method and apparatus for processing color video signals for recording

A first digital data memory is responsive to a first clock signal varying at a rate in accordance with the timing errors contained in a stream of digital data to enter the digital data for temporary storage. The stored digital data is retrieved from storage in the first digital data memory in response to a second clock signal of a stable reference rate. The relative times of entering and retrieving the digital data in the first digital memory are set according to the occurrence of a selected sequence of digital data bits contained in the digital data. The digital data retrieved from the first digital data memory is further temporarily stored in a second digital data memory for an interval determined by the time difference between the occurrence of the selected sequence of digital data bits and the occurrence of a reference time signal.

Digital data rate corrector and time base corrector

Apparatus is disclosed for transmitting through a transmission channel a digital data stream of the type where the position of a level transition within a bit cell determines the information content of the bit cell. As the data stream is transmitted through the transmission channel, degradation of the transitions can occur due to differring response characteristics with respect to level transitions in opposite directions. A pulse for each level transition of the data stream is generated, the pulses converted to a pair of complementary level pulses for transmission, a single level pulse is produced from the transmitted complementary level pulses when the instantaneous level of both said complementary pulses are the same during a transition and thereafter an output signal is provided having a level transition for each pulse.

High bit rate digital data signal transmission system

Apparatus is disclosed for phase locking the output of a voltage controlled oscillator to a self-clocking data pulse stream occurring at a basic predetermined rate, the data stream being of the kind in which the data content is determined by a signal state change located in one of two positions within the data cell interval of the data stream. Each signal state change is defined by a narrow data pulse. The oscillator is controlled by a first means to operate at the predetermined rate when the data pulses are not present and by a second means when the data pulses are present. The second means compares one selected transition of the clock pulses of the oscillator output signal to the position of the data pulse and provides a variable control voltage to the oscillator to adjust its phase so that the the selected clock pulse transition is synchronized to occur at the midpoint of the data pulses.

Phase lock loop for data decoder clock generator

Apparatus is disclosed for producing a full four field NTSC color code sequence of color video information in a manner whereby a continuous nonjittering color video image can be displayed by repeatedly reproducing a recorded two field sequence of color video information. The apparatus is useful in a recording machine which samples the information signal at an odd multiple of the subcarrier frequency and converts the samples to a number of digital data streams and also removes and reinserts horizontal synchronization digital words in the digital component data streams, wherein the horizontal synchronization words are synchronized with the subcarrier. A phase continuous clock signal is used to time the processing of the repetitively reproduced two field sequence of video information. Since the phase of the subcarrier alternates on the second reproducing of a two field sequence, for example, the synchronization word would be misplaced on the second reproduction and would cause a jittering of the video display in the absence of the apparatus of the present invention.

Television subcarrier phase correction for color field sequencing

A circuit for generating a deleted data signal, which is reproduced as a blinking cross in a television picture, to provide thereby visual indication that a storage location in a video frame store is unoccupied, and available for recording therein. The blinking effect is created by interlacing one diagonal line generated in one field with an opposing diagonal line generated in a second field at the 30 Hertz frame rate. The deleted data signal corresponding to the blinking cross is recorded in the deleted track, e.g., the still location thereof, whereby the store can be interrogated and the deleted data signal suitably displayed to indicate the availability and location of the track for subsequent recording.

Circuit for generating a digital, deleted data, blinking cross signal

Apparatus is disclosed for providing a square wave output signal for use in alternating the phase of a sampling clock signal on successive video lines of a video signal having a horizontal blanking interval at the beginning of each video line and a burst of cycles of chrominance subcarrier in each of said horizontal blanking intervals. The square wave output signal changes between first and second levels during alternate video lines, but the signal is always maintained at one of said levels during the occurrence of the bursts of cycles. The square wave signal controls the sampling clock signal generator so that the clock signal is of a first phase while the square wave signal is at the first level and of an opposite phase while the square wave signal is at the second level.

Clock signal generator providing non-symmetrical alternating phase

A method and apparatus is disclosed for restoring the d.c. level of a composite video signal which has a burst of chrominance subcarrier cycles occuring in the horizontal blanking period. The d.c. level of the signal is measured using integrating techniques for a period that corresponds to a whole number of cycles of the chrominance subcarrier and the measured level is used to generate an error signal for adjusting the level to the proper volume. By using a precise whole number of cycles during integration, the d.c. level can be accurately measured.

DC restoration utilizing the color burst signal

A method and apparatus is disclosed for providing a unique digital synchronization word in a generally continually moving digital data stream wherein the data stream represents at least one digital component of a composite video signal having horizontal and vertical blanking intervals, with the horizontal synchronization pulse having been removed therefrom. The apparatus inserts the synchronization word in the horizontal blanking interval, preferably on alternate lines without interrupting the flow of the data stream and discards the information content thereof in the horizontal blanking interval as well as during a significant portion of each vertical blanking interval.

Method and apparatus for inserting synchronizing words in a digitalized

A method and apparatus is disclosed for sampling an analog information signal having an associated carrier signal at precise phase positions with respect to said carrier, which involves sampling the information signal at predetermined phase positions relative to the carrier signal using a phase locked loop to maintain the sampling positions reasonably close to the predetermined phase positions and thereafter examining the discrete samples and generating an error signal that indicates any phase deviation and adjusting the sampling so that the error signal approaches zero and the samples are taken at said precise phase positions.

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Redwood City, CA, United States of America

Luigi C Gallo