Stmicroelectronics S.r.l.

Sgs-thomson Microelectronics S.r.l.

Luigi Bettini

Corrado Villa

Marco Dallabora

Simone Bartoli

Marco Defendi

Lorenzo Bedarida

A Flash EEPROM having negative voltage generator means for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has first positive voltage generator means for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.

Flash EEPROM with on-chip erase source voltage generator

A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.

Pulse generator independent of supply voltage

A Flash EEPROM includes a negative voltage generator for generating a negative voltage to be supplied to control gate electrodes of memory cells for erasing the memory cells. The Flash EEPROM also has a first positive voltage generator for generating a first positive voltage, independent from an external power supply of the Flash EEPROM, to be supplied to source regions of the memory cells during erasing.

A circuit for switching between supply voltages and in particular for non-volatile flash memory devices and of the type comprising a first and a second circuit branch each incorporating a pair of transistors connected in series provides that at least one branch of the circuit be structured with a bridge circuit made up of P-channel MOS transistors. The bridge is made of a first and a second pairs of transistors connected between a first supply voltage reference and a common node. The first pair comprises transistors bigger than the transistors of the second pair while between the transistors making up the second pair is inserted a pair of resistors. Between the pair of resistors there is an interconnection node connected to a corresponding interconnection node between the transistors of the first pair.

Supply voltages switch circuit

A method and a circuit generates a pulse synchronization signal in order to control the reading phase of memory cells in semiconductor integrated, electronic memory devices. The pulse synchronization signal is generated upon sensing a change in logic state on at least one of a plurality of address input terminals of the memory cells to also generate an equalization signal for a sense amplifier. The logic state of said pulse synchronization signal is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal. To this aim, a re-acknowledge circuit portion is provided which is input a corresponding signal to the equalization signal and feedback connected to the output node to drive the discharging of the node with a predetermined delay from the reception of the input signal.

Method and circuit for generating a synchronizing ATD signal

The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps of: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

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Cavenago Brianza, Italy

Luigi Bettini