Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Group Corporation

Saturn Licensing LLC

Lui Sakai

Yasushi Fujinami

Ryoji Ikegaya

Makiko Yamamoto

Keiichi Tsutsui

Tatsuo Shinbashi

Takashi Yokokawa

Kenichi Nakanishi

Hideaki Okubo

Naohiro Adachi

Yasuo Kanda

Satoshi Okada

Yuji Shinohara

Haruhiko Terada

Samuel Asangbeng Atungsiri

Lothar Stadelmeier

Nabil Sven Loghin

Ken Ishii

Joerg Robert

Masahiro Segami

Keizo Hiraga

A memory cell array unit according to an embodiment of the present disclosure includes a memory cell array and a microcontroller. The memory cell array includes an n-bit allocation bit allocated from a memory controller in read/write control, and a redundant bit of one or a plurality of bits not being provided with a switching mechanism that switches as a substitution for a portion of the allocation bit. The microcontroller reads and writes n-bit data from and into the memory cell array using the allocation bit and the redundant bit on the basis of the read/write control from the memory controller.

Memory cell array unit

A memory cell array unit according to an embodiment of the present disclosure includes a microcontroller that performs reading and writing from and into a memory cell array using n-bit allocation memory cells on the basis of read/write control from a memory controller. When a defect is found in one of the n-bit allocation memory cells, the microcontroller writes n−1-bit write data excluding data of a least significant bit among n-bit write data into n−1-bit allocation memory cells excluding the defective allocation memory cell among the n-bit allocation memory cells.

A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.

Semiconductor circuit including latch circuit for error correction

A controller includes a processing circuit that writes each of a plurality of data fragments each including a part of data to be written in one memory chip of a plurality of memory chips each having an error correction function, and reads the data fragments corresponding to the data to be read from the memory chips, a first encoder that encodes the data to be written with an erasure correction code such that each of the data fragments includes a parity, and a first decoder that performs erasure correction by use of a part of the data fragments corresponding to the data to be read according to a completion status or success or failure of error correction on a corresponding part of the data fragments in each of the memory chips, the completion status or the success or failure of the error correction being acquired via a signal line.

Controller and storage device

The present technology relates to a transmission device, a transmission method, a reception device, and a reception method that make it possible to more reliably transmit a transmission control signal. Provided is a transmission device including a transmission unit that includes a first transmission control signal compatible with a first system in a first broadcast signal including a signal of a first content compatible with the first system and a signal of a second content compatible with a second system and transmits the first broadcast signal via a first transmission antenna, and includes a second transmission control signal compatible with the second system in a second broadcast signal including the signal of the second content and transmits the second broadcast signal via a second transmission antenna. The present technology can be applied to, for example, a transmission system compatible with a broadcast system such as an ISDB-T system.

Transmission device, transmission method, reception device, and reception method

A utilization efficiency of a memory is improved. A codeword generation unit generates a codeword in an error detection and correction code from data to be encoded. A write control unit writes one of data obtained by inverting the codeword and the codeword into the memory cell as write data. A read data error correction unit reads out the write data from the memory cell as read data, and corrects an error in the read data. An inversion data error correction unit corrects an error in inversion data obtained by inverting the read data. A correction data output unit, when the number of errors of either only one of the read data and the inversion data does not exceed an error correction capability of the error detection and correction code, selects and outputs the one where the error is corrected as correction data.

Memory controller and method of controlling memory controller

[Object] To sufficiently reduce frequency of error occurrence in memory cells. [Solution] A reading unit reads read data from a memory cell, the read data including an information bit and reversal information for determining whether or not the information bit has been reversed. In addition, an error detection/correction unit detects the presence or absence of an error in the information bit and corrects the error. A data reversing unit reverses the information bit that has the error corrected and the reversal information. Furthermore, a writing unit writes the reversed information bit and the reversed reversal information in the memory cell.

Memory controller, memory system, and memory controller control method

To suppress the degradation of memory cells in a non-volatile memory. A read processing unit performs a read process for reading read data from each of a plurality of memory cells on the basis of a first threshold. An error detection unit detects presence or absence of an error in the read data and specifies memory cells in which the error is present among the plurality of memory cells. A re-read processing unit performs a re-read process for reading data, as re-read data, from the specified memory cells on the basis of a second threshold different from the first threshold. A refresh processing unit rewrites, for a memory cell of which the re-read data has a different value from the read data among the specified memory cells, data with the re-read data as a refresh process.

Memory system, storage device, and method for controlling memory system

An error detection-correction unit reads system information for operating a system from a first memory and performs error detection-correction processing. A control unit supplies the system information to a host computer in a case where the error detection-correction processing is successful. In addition, the control unit reads a backup of the system information from a second memory that is different from the first memory and supplies the backup of the system information to the host computer in a case where the detection-correction processing fails.

Storage control device, storage device, information processing system and storage control method

A memory includes a buffer which retains data, a band conversion unit converts a band of an internal data bus that is used for data transfer between the band conversion unit and the buffer which retains data into a band wider than that of an external data bus that is used for data transfer between the band conversion unit and a memory controller, and an access control unit controls access to a memory cell using the buffer, during a wait time occurring in the internal data bus due to a difference between the band of the internal data bus and the band of the external data bus.

Memory including a band width conversion unit, memory system and memory control method using the same

Provided is a storage control device including: a detection unit which detects a first timing for performing a first rewriting process of performing only a first operation from among the first operation and a second operation, in a memory cell array in which each bit transitions to a first storage state by the first operation and transitions to a second storage state by the second operation; and a request unit which makes a request for the first rewriting process with respect to the memory cell array, when the first timing is detected.

Storage control device, storage device, information processing system, and storage control method

An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data.

Error detection and correction unit, error detection and correction method, information processor, and program

A controller includes: a low-level error correction section configured to execute low-level error correction in which an error in a code word is corrected with use of a predetermined decoding algorithm; and a high-level soft-decision error correction section configured to execute high-level soft-decision error correction in which the error in the code word is corrected with use of a high-level algorithm when the error correction by the low-level error correction section has failed, the high-level algorithm being a soft-decision decoding algorithm having higher error correction capability than error correction capability of the predetermined decoding algorithm.

Controller, information processing system, method of controlling controller, and program

Provided is a memory control device, including a write control unit that sequentially designates a memory block, a write processing unit that writes write data in the designated memory block, a verifying unit that reads read data from the memory block and verifies whether or not the read data matches the write data for each of a plurality of memory cells, a retry inhibiting unit that inhibits a retry process from being performed in a memory cell in which the read data matches the write data among the plurality of memory cells, and a retry control unit that designates at least some memory blocks among the plurality of memory blocks and simultaneously executes the retry process when the read data does not match the write data in any one of the plurality of memory cells in which all the write data is written.

Memory control device, non-volatile memory, and memory control method

An error detection and correction apparatus includes a code word read-out unit to execute read processing to read out a code word including a plurality of code elements by detection of an erasure position as read data from a memory address and to execute re-read processing to read out the code word as re-read data from the memory address after a predetermined time is elapsed from the time to read out the read data; a timing control erasure position detection unit to detect a position of the code element having a value not matched as the erasure position in the code word by determining whether or not the value is matched per the code word in the read data and the re-read data; and an error correction unit to correct an error based on the erasure position in the code word where the erasure position is detected.

Growing community of inventors

Kanagawa, Japan

Lui Sakai