Amkor Technology, Inc.

Other

Amkor Technology Singapore Holding Pte. Ltd.

Texas Instruments Corporation

Ludovico Estrada Bancod

Jin Seong Kim

Robert Lanzone

Jae Ung Lee

Yung Woo Lee

Terry W Davis

Mi Kyeong Choi

Gi Jung Kim

Edwin Joseph Adlam

Gregorio G Dela Cruz

Leocadio M Alabin

Robert Francis Darveaux

Jeffrey Alan Miks

Sean Timothy Crowley

Ahmer Raza Syed

Yeon Ho Choi

William M Anderson

Primitivo A Palasi

Harry J Fogelson

Fidelyn R Canoy

Tom Hu

Nhun Thun Kham

Eulogia A Niones

Glenn A Rinne

Timothy Lee Olson

Kurt Peter Wachtler

Christopher J Berry

Akito Yoshida

Dean Zehnder

Won Dai Shin

Ian Kent

Marnie Ann Mattei

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.

Semiconductor package and manufacturing method thereof

Methods for copper pillar protection may include forming a metal post over a contact on a semiconductor die, where the metal post comprises a sidewall. A metal cap may be formed on the metal post and may be wider than the width of the metal post. A solder bump may be formed on the metal cap, and a conformal passivation layer may be formed on at least the sidewall of the metal post. The metal cap may be rounded shaped or rectangular shaped in cross-section. The metal post and the metal cap may comprise copper. The metal cap may comprise a copper layer and a nickel layer. The seed metal layer may comprise one or more of titanium, tungsten, and copper. The conformal passivation layer may comprise a nonwettable polymer. Horizontal portions of the conformal passivation layer may be removed utilizing an anisotropic etch such as a plasma etch.

Copper pillar sidewall protection

A flex circuit package includes a package body enclosing an electronic component and a first surface of the substrate. Columns are physically and electrically connected to first traces of the substrate, the columns extending through the package body. A flexible circuit connector has first terminals connected to the columns. The flexible circuit connector further includes second terminals that provide an electrical interconnection structure for electrical connection to a second electronic component structure. By connecting the flexible circuit connector to the columns extending through the package body, special routing of traces of the substrate of the flex circuit package to provide an interface for the flexible circuit connector is avoided.

Flex circuit package and method

A method of forming a stackable plasma cleaned via package includes forming interconnection balls on terminals. The interconnection balls are encapsulated in a package body, e.g., molding compound. Via apertures are formed through the package body to expose the interconnection balls, wherein a contamination is formed on the interconnection balls. The contamination is removed using a plasma cleaning process. By removing the contamination, robust reflow of the interconnection balls is insured thus maximizing yield. Further, the plasma cleaning process is a cost efficient high volume process with no adverse effect on package reliability.

Stackable plasma cleaned via package and method

A method of forming a stackable treated via package includes coupling interconnection balls to terminals. The interconnection balls are encapsulated in a package body. Via apertures are formed in the package body to expose the interconnection balls. The interconnection balls are treated to form treated interconnection balls comprising treated surfaces. The treated interconnection balls of the stackable treated via package enhance bonding with interconnection balls of a stacked electronic component package thus maximizing yield.

Stackable treated via package and method

A semiconductor package comprising a leadframe. The leadframe itself comprises an outer frame portion which defines a central opening. Disposed within the central opening is a die pad which defines opposed, generally planar top and bottom die pad surfaces and a peripheral edge. Connected to and extending between the outer frame portion and the peripheral edge of the die pad is at least one tie bar of the leadframe. The leadframe also includes a plurality of leads which are connected to the outer frame portion and extend into the opening at least partially about the die pad in spaced relation to the peripheral edge thereof. Each of the leads includes opposed, generally planar top and bottom lead surfaces, with at least two of the leads comprising corner leads which extend along opposed sides of the tie bar. Each of the corner leads further defines an angularly offset distal portion which extends along and in spaced relation to the tie bar.

Offset etched corner leads for semiconductor package

A memory card comprising a substrate which has a plurality of contacts, at least one die pad, and a plurality of traces. The contacts, the die pad and the traces are disposed in spaced relation to each other and each define opposed first and second surfaces. Mounted to the first surface of the die pad is at least one electronic component which is electrically connected to at least one of the contacts either directly or via one or more of the traces. A first encapsulation part covers the second surfaces of the die pad and the traces, with the second surfaces of the contacts being exposed in the first encapsulation part. A second encapsulation part covers the electronic component and the first surfaces of the die pad, the contacts, and the traces. The first and second encapsulation parts collectively define a body of the memory card which includes a bottom surface having the second surfaces of the contacts exposed therein.

Secure digital memory card using land grid array structure

A method of fabricating a semiconductor package comprising the step of providing a leadframe strip which defines a strip plane and a multiplicity of leadframes. Each of the leadframes includes an outer frame defining a central opening and a die pad disposed within the central opening. Each leadframe further includes a plurality of leads which are attached to the outer frame and extend toward the die pad in spaced relation to each other. The outer frames are integrally connected to each other and collectively define connecting bars which extend in multiple rows and columns and define saw streets. Semiconductor dies are attached to respective ones of the die pads, with the semiconductor dies being mechanically and electrically connected to the leads of respective ones of the leadframes. Thereafter, an encapsulant material is applied to the leadframe strip to form at least one mold cap which at least partially encapsulates the leadframes, the semiconductor dies, and the conductive wires. The leadframe strip and the mold cap collectively define a package strip. Isolation cuts are formed through the package strip along at least some of the saw streets to effectively electrically isolate the leadframes from each other.

Leadframe strip having enhanced testability

A lead frame strip for use in the manufacture of integrated circuit chip packages. The strip comprises at least one array defining a multiplicity of lead frames. The lead frames each include an outer frame defining a central opening having a die pad disposed therein. Attached to the outer frame and extending toward the die pad in spaced relation to each other are a plurality of leads. The outer frames are integrally connected to each other such that the lead frames are arranged in a matrix wherein the leads thereof extend in multiple rows and columns. The leads of the lead frames within each of the rows and columns are arranged in sets which are disposed in spaced relation to each other. A plurality of openings are formed within the strip between and in alignment with the leads of each of the lead frames within each of the rows and columns. The leads of each of the lead frames within each of the rows and columns and the openings collectively define saw streets for cutting the strip in a manner separating the lead frames from each other.

Reduced copper lead frame for saw-singulated chip package

A method of fabricating semiconductor packages from a lead frame strip which includes a mold cap applied to one side thereof, and defines a multiplicity of lead frames integrally connected to each other by connecting bars which extend in multiple rows and columns and define saw streets. In the singulation method of the present invention, the mold cap is sawed along the saw streets to expose the connecting bars. Thereafter, the connecting bars are chemically etched to separate the lead frames from each other.

Saw and etch singulation method for a chip package

Growing community of inventors

Chandler, AZ, United States of America

Ludovico Estrada Bancod