Imec Vzw

Imec

Nxp B.v.

Katholieke Universiteit Leuven

STMicroelectronics

Université François Rabelais

University of South Toulon Var

Stmicroelectronics S.a. Universite Francois Rabelais

University of Ghent

Ludovic Goux

Dirk Wouters

Judit Gloria Lisoni Reyes

Thomas Gille

Gouri Sankar Kar

Monique Gervais

Attilio Belmonte

Mihaela Ioana Popovici

Romain Delhougne

Davide Francesco Crotti

Judit G Lisoni

Robin Degraeve

Daniele Garbin

Dirk J C C M Wouters

Luca Di Piazza

Christian Turquat

Christophe Muller

Judith Lisoni

Judit Lisoni Reyes

Lorene Courtade

Andrea Fantini

Chao-Yang Chen

Wouter Devulder

Karl Opsomer

The disclosed technology generally relates to integrated circuit (IC) devices and more particularly to IC devices based on metal ion migration, and to manufacturing of the IC devices. In one aspect, a method of manufacturing an integrated electronic circuit, which includes at least one component based on metal ion migration and reduction, allows improved control of an amount of the metal which is incorporated into the component. This amount is produced from a metal supply layer and transferred into a container selectively with respect to the rest of the component. The container is configured as part of an electrolyte portion or active electrode in the final component. The method is compatible with two-dimensional and three-dimensional configurations of the component.

Integrated circuit devices based on metal ion migration and methods of fabricating same

The disclosed technology relates to a structure for use in a metal-insulator-metal capacitor. In one aspect, the structure comprises a bottom electrode formed of a Ru layer. The Ru layer has a top surface characterized by a grazing incidence X-ray diffraction spectrum comprising a first intensity and a second intensity, the first intensity corresponding to a diffracting plane of Miller indices (0 0 2) being larger than the second intensity corresponding to a diffracting plane of Miller indices (1 0 1). The structure further comprises an interlayer on the top surface of the Ru layer, the interlayer being formed of an oxide of Sr and Ru having a cubic lattice structure, and a dielectric layer on the interlayer, the dielectric layer being formed of an oxide of Sr and Ti.

Structure for use in a metal-insulator-metal capacitor

In one aspect, a method for manufacturing a three-dimensional (3D) semiconductor device is disclosed. It includes providing a vertical stack of alternating layers of a first layer type and a second layer type, and providing a first trench and a second trench adjacent the vertical stack. The first trench and the second trench can define a fin. The method further can include recessing the first layer type to form recesses extending into the fin, providing a first electrode in individual ones of the recesses, and providing a second electrode in the first trench and the second trench. The method further can include providing, for individual ones of the recesses, a lateral stack including a memory element, a middle electrode, and a selector element. The lateral stack can extend between the first electrode and the second electrode, thereby forming a memory device.

Three-dimensional semiconductor device and method of fabricating same

The disclosed technology generally relates to a switching device and more particularly to a switching device based on an active portion capable of switching from an insulating state to a conductive state. In an aspect, a switching device comprises an active portion interposed between two electrodes and capable of switching from an insulating state to a conducting state when a voltage higher than a threshold value is applied between the two electrodes. The threshold value is lowered by a dielectric permittivity distribution which produces a concentration of electrical field at a location within the active portion. Thus, the switching device may be devoid of a third control electrode.

Switching device with active portion configured to switch between insulating state and conducting state

A Conductive Bridge Random Access Memory (CBRAM) device comprising an insulating electrolyte element sandwiched between a cation supply electrode and a bottom electrode, whereby the conductivity &#x3c3; of the cation provided by the cation supply electrode in the electrolyte element increases towards the bottom electrode.

Conductive bridging memory device

A method is disclosed for operating a Conductive Bridge Random Access Memory (CBRAM) device that includes an electrolyte element sandwiched between a cation supply top electrode and a bottom electrode. The method comprises conditioning the CBRAM device by applying a forming current pulse having a pulse width (t) of 100 ns or less and a pulse amplitude (I) of 10 uA or less, and when programming, setting the conditioned CBRAM device to a Low Resistance State (LRS) by applying a set current pulse having a pulse width (t) of 100 ns or less and a pulse amplitude (I) equal to or larger than the forming current pulse amplitude (I).

Method for operating a conductive bridging memory device

A conductive-bridge random access memory device is disclosed comprising a second metal layer configured to provide second metal cations; a layer of insulator adjacent to the second metal layer; the layer of insulator comprising a layer of first insulator and a layer of second insulator; the layer of second insulator being adjacent to the second metal layer; a first metal layer adjacent to the layer of first insulator, the first metal layer being opposite to the second metal layer; wherein the density of the layer of second insulator is higher than the density of the layer of first insulator.

Self-isolated conductive bridge memory device

Resistive memory elements and arrays of resistive memory elements are disclosed. In one embodiment, a resistive memory element includes a top electrode element lying in a plane parallel to a reference plane, and having, in perpendicular projection on the reference plane, a top electrode projection; a bottom electrode element lying in a plane parallel to the reference plane, and having, in perpendicular projection on the reference plane, a bottom electrode projection; and an active layer with changeable resistivity interposed between the top electrode element and the bottom electrode element. The top electrode projection and the bottom electrode projection overlap in an overlapping region that comprises a corner of the top electrode projection and/or a corner of the bottom electrode projection, and an area of the overlapping region constitutes less than 10% of a total projected area of the top electrode element and the bottom electrode element on the reference plane.

Resistive memory element and related control method

A memory device comprises an array of memory cells for storing data and a voltage application unit for applying voltages to the cells for writing data to the cells. Each memory cell has a first layer comprising copper in contact with a second layer comprising a chalcogenide material. The voltage application unit is arranged to write data by switching each cell between a first resistance state and a second, lower, resistance state. The voltage application unit is arranged to switch a cell to the first resistance state by applying a potential difference across the first and second layers such that the potential at the first layer is higher than the potential at the second layer by 0.5 volts or less. The voltage application unit is arranged to switch a cell to the second resistance state by applying a potential difference across the first and second layers such that the potential at the second layer is higher than the potential at the first layer by 0.5 volts or less. The current flow when switching between resistance states is less than 10 &#x3bc;A. The memory cells of the device can be toggled between the resistance states, and the resistance states are non-volatile.

Non-volatile memory device

A resistive switching non-volatile memory element is disclosed comprising a resistive switching metal-oxide layer sandwiched between and in contact with a top electrode and a bottom electrode, the resistive switching metal oxide layer having a substantial isotropic non-stoichiometric metal-to-oxygen ratio. For example, the memory element may comprise a nickel oxide resistive switching layer sandwiched between and in contact with a nickel top electrode and a nickel bottom electrode whereby the ratio oxygen-to-nickel of the nickel oxide layer is between 0 and 0.85.

Method for manufacturing a resistive switching memory cell comprising a nickel oxide layer operable at low-power and memory cells obtained thereof

The present disclosure provides a method for controlled formation of the resistive switching layer in a resistive switching device. The method comprises providing a substrate () comprising the bottom electrode (), providing on the substrate a dielectric layer () comprising a recess () containing the metal for forming the resistive layer (), providing on the substrate a dielectric layer () comprising an opening () exposing the metal of the recess, and forming the resistive layer in the recess and in the opening.

Method for controlled formation of the resistive switching material in a resistive switching device and device obtained thereof

A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.

Method for manufacturing a resistive switching memory device and devices obtained thereof

A phase-change-memory cell is provided which comprises two insulated regions formed in a first phase-change material connected by a region formed in a second phase-change material. The crystallization temperature of the second phase-change material is below the crystallization temperature of the first phase-change material. By locally changing the material properties using a second PCM material, which switches phase at a lower temperature, a localized 'hot spot' is obtained.

Phase-change memory cell having two insulated regions

The present disclosure is related to non-volatile memory devices comprising a reversible resistivity-switching layer used for storing data. The resistivity of this layer can be varied between at least two stable resistivity states such that at least one bit can be stored therein. In particular this resistivity-switching layer is a metal oxide or a metal nitride. A resistivity-switching non-volatile memory element includes a resistivity-switching metal-oxide layer sandwiched between a top electrode and a bottom electrode. The resistivity-switching metal-oxide layer has a gradient of oxygen over its thickness. The gradient is formed in a thermal oxidation step. Set and reset voltages can be tuned by using different oxygen gradients.

Method for manufacturing a memory element comprising a resistivity-switching NiO layer and devices obtained thereof

A phase-change-material memory cell is provided. The cell comprises at least one patterned layer of a phase-change material, and is characterized in that this patterned layer comprises at least two regions having different resistivities. If the resistivity of the phase-change material is higher in a well-defined area with limited dimensions ('hot spot') than outside this area, then, for a given current flow between the electrodes, advantageously more Joule heat will be generated within this area compared to the area of the phase-change material where the resistivity is lower.

Growing community of inventors

Hannut, Belgium

Ludovic Goux