Seagate Technology Incorporated

Lsi Corporation

Ludovic Danjean

Erich Franz Haratsch

Sundararajan Sankaranarayanan

Abdelhakim Alhussien

Ivana Djurdjevic

Thuy Van Nguyen

Ara Patapoutian

Zongwang Li

Zheng Wang

Abdel Hakim S Alhussien

Abdel Hakim Alhussien

Systems and methods presented herein provide for mitigating errors in a storage device. In one embodiment, a storage system includes a storage device comprising a plurality of storage areas operable to store data, and a controller operable to evaluate operating conditions of the storage device, to perform a background scan on a first of the storage areas to characterize a read retention of the first storage area, and to adjust a read signal of the first storage area based on the characterized read retention and the operating conditions of the storage device.

Mitigating data errors in a storage device

Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.

Storage area retirement in a storage device

An apparatus includes an interface and a control circuit. The interface may be configured to process transfers to/from a medium. The control circuit may be configured to generate a trapping set list of trapping sets of a low-density parity check code, classify bit positions of the trapping sets as belonging to either a user bits field or a parity bits field of a codeword, encode data using the low-density parity check code to generate the codeword, and present the codeword to the interface to transfer the codeword to the medium. The generation of the codeword may include at least one of a shortening or a puncturing of bit locations in the codeword in response to the classifying of the bit positions of the trapping sets. All of the data may be held in the bit locations of the codeword other than the bit locations that are shortened or punctured.

Mitigation of error correction failure due to trapping sets

Apparatus and method for reducing read disturbed data in a non-volatile memory (NVM). Read operations applied to a first location in the NVM are counted to accumulate a read disturb count (RDC) value. Once the RDC value reaches a predetermined threshold, a flag bit is set and a first bit error statistic (BES) value is evaluated. If acceptable, the RDC value is reduced and additional read operations are applied until the RDC value reaches the predetermined threshold a second time. A second BES value is evaluated and data stored at the first location are relocated if an unacceptable number of read errors are detected by the second BES value. Different thresholds are applied to the first and second BES values so that fewer read errors are acceptable during evaluation of the second BES value as compared to the first BES value.

Read disturb detection based on dynamic bit error rate estimation

Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.

Adaptive read threshold voltage tracking with charge leakage mitigation using charge leakage settling time

Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time; shift the plurality of read reference voltages using the at least one reference voltage offset; and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after a predefined time interval since a programming of the multi-level memory cells.

Adaptive read threshold voltage tracking with charge leakage mitigation using threshold voltage offsets

Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.

Read retry operations with estimation of written data based on syndrome weights

Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.

Low density parity check (LDPC) decoder with pre-saturation compensation

An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.

Read retry operations in a memory employ likelihood value assignments that change sign at different read voltages for a plurality of read retry operations. A method for multiple read retries of a memory comprises reading a codeword using a first read voltage to obtain a first read value; mapping the first read value to first likelihood values based on a first likelihood value assignment that changes sign substantially at the first read voltage; reading the codeword using a second read voltage to obtain a second read value, wherein the second read voltage is shifted from the first read voltage to compensate for an expected change in analog voltages; and mapping the second read value to second likelihood values based on a second likelihood value assignment, wherein the second likelihood value assignment changes sign substantially at the second read voltage. Read data is optionally generated using iterative decoding of the codeword based on the first likelihood values and/or the second likelihood values.

Read retry operations where likelihood value assignments change sign at different read voltages for each read retry

Methods and apparatus are provided for read retry operations with read reference voltages ranked for different page populations of a memory. One method comprises obtaining a plurality of rankings of a plurality of read reference voltages for a plurality of page populations, wherein the rankings are based on a predefined performance metric; and reading a codeword from the memory a plurality of times, wherein each of the read operations uses a different one of the plurality of read reference voltages selected based on the rankings of the plurality of read reference voltages. The performance metric comprises, for example, a bit error rate, a bit polarity disparity, a substantially minimal syndrome weight and/or measures of an average system latency or a tail latency. The ranking is optionally based on a size of the page populations that had each of the ranked read reference voltages. Channel estimation is performed separately for each of the plurality of page populations.

Read retry operations with read reference voltages ranked for different page populations of a memory

Methods and apparatus are provided for detection and decoding in flash memories with selective binary and non-binary decoding. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits from one or more pages of the flash memory device; converting; the one or more read values for the plurality of bits to a non-binary log likelihood ratio based on a probability that a given data pattern was written to the plurality of bits when a particular pattern was read from the plurality of bits; and jointly decoding the plurality of bits using the non-binary log likelihood ratio, wherein the pages are encoded independently.

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San Jose, CA, United States of America

Ludovic Danjean