Nxp B.v.

Koninklijke Philips Corporation N.v.

St-ericsson Sa

Nxp Usa, Inc.

Lucien Johannes Breems

Muhammed Bolatkale

Robert Rutten

Shagun Bajoria

Chenming Zhang

Johannes Hubertus Antonius Brekelmans

Fabio Sebastiano

Robert Henrikus Margaretha Van Veldhoven

Manfred Zupke

Pierluigi Cenci

Eise Carel Dijkmans

Dominicus Martinus Wilhelmus Leenaerts

Massimo Ciacci

Martin Kessel

Raf Lodewijk Jan Roovers

Salvatore Drago

Hendrik Van Der Ploeg

Marcello Ganzerli

Bernard Burdiek

Mohammed Abo Alainein

Jan Niehof

George Anthony Brock-Fisher

Andries Pieter Hekstra

Alessio Filippi

Arie Geert Cornelis Koppelaar

Bram Nauta

Jan Van Sinderen

Gary Allen Schwartz

Steven Russell Freeman

Ovidiu Bajdechi

Evert-Jan Pol

Theodore Philip Fazioli

Johan Frederik Witte

Henricus J Kunnen

Qilong Liu

Soheil Bahrami

Robert Henrikus Van Veldhoven

Albertus Willibrordus Oude Essink

Dominicus Martinues Wilhelmus Leenaerts

Jingjing Hu

A circuitis described comprising (i) a first digital-to-analog converter, (ii) a second digital-to-analog converter, (iii) a plurality of unit elements, and (iv) switching circuitry. The switching circuitryis adapted so that in a first switching state, a set of unit elementsof the plurality of unit elementsforms part of the first digital-to-analog converter, and in a second switching state, the set of unit elementsforms part of the second digital-to-analog converter. Furthermore, a corresponding method of operating a circuitis described.

Circuit with two digital-to-analog converters and method of operating such the circuit

There is described an analog-to-digital converter, ADC, device (), comprising:

Operating an analog-to-digital converter device

Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.

Shuffler-free ADC error compensation

A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.

System and method of reducing delta-sigma modulator error using force-and-correction

A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

Signal shaping for compensation of metastable errors

A high-speed comparator circuit is provided. The circuit includes an amplifier portion, a latch portion, and a negative capacitance portion. The amplifier portion includes an input coupled to receive an analog signal and an output. The latch portion is coupled to the amplifier portion. The latch portion is configured to provide at the output a digital value based on the analog signal. The negative capacitance portion is coupled to the output. The negative capacitance portion is configured to cancel parasitic capacitance coupled at the first output.

Comparator with negative capacitance compensation

A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

System and method of replicating and cancelling chopping folding error in delta-sigma modulators

A sigma delta modulator comprises an input configured to receive an input analog signal; a summing junction configured to subtract a feedback analog signal from the input analog signal; a first stage including a low pass filter coupled to the summing junction, wherein the low pass filter is configured to generate a first filtered signal; a second stage coupled to the low pass filter, configured to generate a second filtered signal by an active filter; a back-end stage coupled to the second stage, wherein the back-end stage comprises an analog to digital converter configured to convert the 2filtered signal to a digital output signal by sampling at a predetermined sampling frequency (fs); and a feedback path for routing the digital output signal to the summing junction, wherein the feedback path comprises a digital to analog converters, DAC, converting the digital output signal to the feedback analog signal.

Sigma delta modulator and method therefor

A digital conversion system including a sigma-delta converter, a tone generator that generates injects a tone signal into the conversion path of the sigma-delta converter at a frequency that is outside operating signal frequency range, a tone detector that isolates and detects a level of the injected tone signal and provides a corresponding tone level value, a tone ratio comparator that converts the tone level value into a tone level ratio and that compares the converted tone level ratio with an expected tone level ratio to provide an error signal, and a loop controller that converts the error signal to a correction signal to adjust a loop filter frequency the sigma-delta converter. Tones may be serially injected one at a time or simultaneously in parallel for determining a measured tone level ratio for comparison with a corresponding one of multiple stored expected tone level ratios.

System and method of calibration of sigma-delta converter using tone injection

A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

System and method of calibration of sigma-delta converter using injected signal correlation

The present disclosure relates generally to techniques for continuous-time sigma-delta analog-to-digital converter (ADC). The continuous-time sigma-delta ADC may include a feed-forward capacitor in parallel with a current-steering excess loop delay (ELD) digital-to-analog converter (DAC), and by creating a zero in a transfer function of a Gm cell, both an ELD feedback loop settling and a main feedback loop may be recovered. As a result, the performance and stability of the continuous-time sigma-delta ADC can be achieved. Additionally, a summation node in the continuous-time sigma-delta ADC may offer flexibility in the architecture design of the continuous-time sigma-delta ADC.

Techniques for high-speed excess loop delay compensation in sigma-delta analog-to-digital converters

The present disclosure relates generally to techniques for linearizing a digital-to-analog converter (DAC) in a continuous-time sigma-delta ADC. A sigma-delta ADC may be configured with a multibit quantizer for various applications. These applications may require wide-bandwidth high-resolution high-linearity power-efficient ADCs. In some embodiments, a mismatch of a multibit DAC might result in a bottleneck for achieving high linearity performance. Some linearization techniques may achieve high linearity performance. However, for a high-speed sigma-delta ADC, the DAC is configured to be part of a feedback loop. Existing linearization techniques often increase the delay in the feedback loop, which is not desired. Various aspects of the present disclosure provide improvement to linearization techniques by changing the references of the multibit quantizer. As a result, this reduces delay in the feedback loop of the sigma-delta modulator, which is beneficial for high-speed sigma-delta ADCs.

Techniques for linearizing digital-to-analog converters in sigma-delta analog-to-digital converters

A N-bit continuous-time sigma-delta modulator, SDM, () includes an input configured to receive an input analog signal (); a first summing junction () configured to subtract a feedback analog signal () from the input analog signal (); a loop filter () configured to filter an output signal from the first summing junction (): an N-bit analog-to-digital converter, ADC, comprising at least one 1-bit ADC configured to convert the filtered analog output signal () to a digital output signal () where each 1-bit ADC comprises at least one pair of comparator latches (); and a feedback path () for routing the digital output signal to the first summing junction (). The feedback path () includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal () to an analog form. The ADC comprises or is operably coupled to, a calibration circuit () coupled to an input and an output of the at least one pair of comparator latches () and configured to apply respective calibration signals to individual comparator latches of the at least one pair of comparator latches () in a time-Interleaved manner, and calibrate a comparator error of the comparator latches in response to a latched output of the respective calibration signals.

Sigma delta modulator, integrated circuit and method therefor

An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

Offset compensation in ADC circuitry

Interference cancellation is provided, according to certain aspects, by a filter, a signal detection circuit, synthesis circuitry and signal-generation circuitry. The filter is used to filter an incoming signal having an associated signal-to-noise metric and to output therefrom a filtered signal having an interference attribute of the incoming signal by amplification and/or isolation. The signal detection circuit is used to detect the interference attribute in the filtered signal. The synthesis circuitry is used to synthesize interference in the incoming signal based on the interference attribute. The signal-generation circuitry is used to generate, in response to the synthesized interference in the incoming signal, a filtered version of the incoming signal which provides an improved signal-to-noise metric.

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Eindhoven, Netherlands

Lucien Johannes Breems