Nxp B.v.

Lucie A Rousseville

Patrice Gamand

Serge Bardy

Dominique Yon

Philippe Le Duc

Sebastien Jacqueline

David Desmortreux

The present invention relates to a method and system for testing integrity of a passivation layer () covering a semiconductor device. A structured layer of electrically conducting material () is deposited onto at least a portion of a top surface of a substrate () of the semiconductor device. The structured layer () comprises a plurality of bands () connected to at least two contacts () and disposed on the at least a portion of the top surface such that one of consecutive bands () and consecutive portions of the bands () are connected to different contacts (). A passivation layer () is deposited onto the at least a portion of the top surface of the substrate () and the structured layer () such that material of the passivation layer() is disposed between the bands of conducting material () and on top of the structured layer (). Electrically conducting material is then deposited onto the passivation layer () and a resistance is measured between the at least two contacts (). An indication with respect to integrity of the passivation layer () is determined in dependence upon the measured resistance.

Embedded structure for passivation integrity testing

Semiconductor device with a patterned pad metal layer and a patterned under-bump metallization layer being mutually electrically connected in a common contact area. The semiconductor device includes a first test structurefor determining a contact resistance between the patterned metallization layer and the patterned pad metal layer in the common contact areas. The first test structure includes a pad metal layer portionand a metallization layer portionbeing in electrical communication with the pad metal layer portionthrough the common contact area. The first test structurefurther includes connection areasthat are electrically connected with each other substantially via the common contact area. Upon application of a current between the connection areasa voltage drop occurs that is representative for a voltage drop over the common contact area

Semiconductor device and wafer with a test structure and method for assessing adhesion of under-bump metallization

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Waldolwisheim, France

Lucie A Rousseville