Texas Instruments Corporation

Luciano Talamonti

Michael C Smayling

Giulio Giuseppe Marotta

Giuliano Imondi

Giuseppe Savarese

Giulio Porrovecchio

A charge pump (10) uses Schottky diodes (12) coupled to clock signals (.phi..sub.1 and .phi..sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

Charge pump circuit with capacitors

A charge pump (10) uses Schottky diodes (12) coupled to clock signals (o.sub.1 and o.sub.2) via respective capacitors (14a-d). Regulation and control circuitry 18 provides a stable voltage output and controls the clock circuitry (16).

Charge pump circuit with field oxide regions

Method of forming a charge pump circuit

Data processing system implementing architecture of a neural network which is subject to a learning process, wherein the data processing system includes n.times.n synapses arranged in an array of j rows and i columns. A plurality of operational amplifiers respectively corresponding to the rows of the array are provided, with each operational amplifier defining a neuron. The input terminals of all of the synapses arranged in a respective column of the array are connected together and define n inputs of the neural network. The output terminals of the synapses arranged in a respective row of the array are connected together and serve as the inputs to a corresponding one of the plurality of operational amplifiers. Each synapse includes a capacitor connected between ground potential and the input terminal for weighting the synapse by storing a weighting voltage applied thereto. A random access memory has digitally stored voltage values for weighting all of the synapses. A plurality of digital-analog converters, one for each column of the array of synapses, are connected to the random access memory for converting the digital voltage values for weighting the synapses into analog voltage values. The digital-analog converters provide respective outputs to the weighting terminals of the synapses of a column via respective electronic switches for each synapse. Each row of the array includes a bistable circuit for driving the respective electronic switches under the control of a control section which also provides function commands and data to the random access memory.

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Rieti, Italy

Luciano Talamonti