Soitec

S.o.i.tec Silicon on Insulator Technologies

Luciana Capello

Isabelle Bertrand

Oleg Kononchuk

Marcel Broekaart

Didier Landru

Walter Schwarzenbach

Daniel Delprat

Eric Neyret

Frédéric Allibert

Christophe Figuet

Eric Desbonnets

Patrick Reynaud

Christelle Veytizou

Isabelle Huyet

Alexandra Abbadie

Young-Pil Kim

Norbert Colombet

Eric Desbonnet

A handle substrate for a composite structure comprises a base substrate including an epitaxial layer of silicon on a monocrystalline silicon wafer obtained by Czochralski pulling, a passivation layer on and in contact with the epitaxial layer of silicon, and a charge-trapping layer on and in contact with the passivation layer. The monocrystalline silicon wafer of the base substrate exhibits a resistivity of between 10 and 500 ohm·cm, while the epitaxial layer of silicon exhibits a resistivity of greater than 2000 ohm·cm and a thickness ranging from 2 to 100 microns. The passivation layer is amorphous or polycrystalline. A method is described for forming such a substrate.

Method for forming a handling substrate for a composite structure intended for RF applications and handling substrate

A support for a semiconductor structure includes a base substrate, a first silicon dioxide insulating layer positioned on the base substrate and having a thickness greater than 20 nm, and a charge trapping layer having a resistivity higher than 1000 ohm&#xb7;cm and a thickness greater than 5 microns positioned on the first insulating layer.

Support for a semiconductor structure

A method of fabrication of a semiconductor element includes a step of rapid heat treatment in which a substrate comprising a base having a resistivity greater than 1000 Ohm&#xb7;cm is exposed to a peak temperature sufficient to deteriorate the resistivity of the base. The step of rapid heat treatment is followed by a curing heat treatment in which the substrate is exposed to a curing temperature between 800&#xb0; C. and 1250&#xb0; C. and then cooled at a cooldown rate less than 5&#xb0; C./second when the curing temperature is between 1250&#xb0; C. and 1150&#xb0; C., less than 20&#xb0; C./second when the curing temperature is between 1150&#xb0; C. and 1100&#xb0; C., and less than 50&#xb0; C./second when the curing temperature is between 1100&#xb0; C. and 800&#xb0; C.

Method of fabrication of a semiconductor element comprising a highly resistive substrate

A process for the manufacture of a semiconductor element includes a stage of rapid heat treatment of a substrate comprising a charge-trapping layer, which is capable of damaging an RF characteristic of the substrate. The rapid heat treatment stage is followed by a healing heat treatment of the substrate between 700&#xb0; C. and 1,100&#xb0; C., for a period of time of at least 15 seconds.

Process for the manufacture of a semiconductor element comprising a layer for trapping charges

The invention relates to an electronic device for radiofrequency or power applications, comprising a semiconductor layer supporting electronic components on a support substrate, wherein the support substrate comprises a base layer having a thermal conductivity of at least 30 W/mK and a superficial layer having a thickness of at least 5 &#x3bc;m, the superficial layer having an electrical resistivity of at least 3000 Ohm&#xb7;cm and a thermal conductivity of at least 30 W/mK. The invention also relates to two processes for manufacturing such a device.

Electronic device for radiofrequency or power applications and process for manufacturing such a device

The invention relates to a method for fabricating a semiconductor on insulator substrate, in particular a silicon on insulator substrate by providing a source substrate, providing a predetermined splitting area inside the source substrate by implanting atomic species, bonding the source substrate to a handle substrate, detaching a remainder of the source substrate from the source-handle component at the predetermined splitting area to thereby transfer a device layer of the source substrate onto the handle substrate, and thinning of the device layer. To obtain semiconductor on insulator substrates with a reduced Secco defect density of less than 100 per cmthe implanting is carried out with a dose of less than 2.3&#xd7;10atoms per cmand the thinning is an oxidation step conducted at a temperature of less than 925&#xb0; C.

Method for fabricating a semiconductor on insulator substrate with reduced Secco defect density

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Grenoble, France

Luciana Capello