Intel Corporation

Lucian Shifren

Jack T Kavalieros

Justin K Brask

Cory E Weber

Martin D Giles

Steven M Cea

Robert S Chau

Brian S Doyle

Willy Rachmady

Matthew V Metz

Mark L Doczy

Suman Datta

Titash Rakshit

Been Y Jin

Everett X Wang

Mark Stettler

Philippe Matagne

A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.

Epitaxial silicon germanium for reduced contact resistance in field-effect transistors

A process includes planarizing a microelectronic device that includes a gate stack and adjacent trench contacts. The process also includes removing a gate spacer at the gate stack and replacing the gate spacer with a dielectric that results in a lowered overlap capacitance between the gate stack and an adjacent embedded trench contact.

Replacement spacers for MOSFET fringe capacitance reduction and processes of making same

A transistor may be formed of different layers of silicon germanium, a lowest layer having a graded germanium concentration and upper layers having constant germanium concentrations such that the lowest layer is of the form SiGe. The highest layer may be of the form SiGeon the PMOS side. A source and drain may be formed of epitaxial silicon germanium of the form SiGeon the PMOS side. In some embodiments, x is greater than y and z is greater than x in the PMOS device. Thus, a PMOS device may be formed with both uniaxial compressive stress in the channel direction and in-plane biaxial compressive stress. This combination of stress may result in higher mobility and increased device performance in some cases.

Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress

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Hillsboro, OR, United States of America

Lucian Shifren