Cadence Design Systems, Inc.

Lucas Martins Chaves

Georgia Penido Safe

Vincent Gregory Reynolds

Yumi Monma

Mirlaine Aparecida Crepalde

Tulio Paschoalin Leao

Fernanda Augusta Braga

Felipe Althoff

Arthur Ribeiro Araujo

Petros Daniel Fernandes De Medeiros Félix

Andrei Dos Santos Silva

Pablo Nunes Agra Belmonte

Pedro Bruno Neri Silva

Julia Pinheiro De Oliveira

Mariana Ferreira Marques

A formal verification EDA application can be configured to receive a circuit design of an IC chip. The circuit design of the IC chip comprises a set of properties for the IC chip and constraints for the IC chip. The formal verification EDA application generates an array of CNF files based on the circuit design of the IC chip. Each CNF file can include a Boolean expression that characterizes a selected property of the set of properties and data fields characterizing initial states for literals in the Boolean expression and the constraints of the IC chip. The formal verification application can also be configured to output the array of CNF files to a hardware prototyping platform. The hardware prototyping platform can be configured to execute a hardware instantiated SAT solver for the Boolean expression in each CNF file in the array of CNF files.

Formal verification with EDA application and hardware prototyping platform

The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.

System, method, and computer program product for determining suitability for formal verification

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Belo Horizonte, Brazil

Lucas Martins Chaves