Stmicroelectronics S.r.l.

Sgs-Thomson Microelectronics S.r.l.

Luca Zanotti

Maurizio Bacchetta

Flavio Francesco Villa

Paolo Ferrari

Marco Ferrera

Matteo Perletti

Luca Seghizzi

Igor Varisco

Giorgio De Santi

Andrea Nomellini

Giuseppe Queirolo

Laura Bacci

Bruno Murari

Pietro Montanini

Giuseppe Paolo Crisenza

Michele Palmieri

Marta Mottura

Lucia Zullino

Paolo Riboli

Martina Scolari

A thermoelectric generator includes a substrate and one or more thermoelectric elements on the substrate and each configured to convert a thermal drop across the thermoelectric elements into an electric potential by Seebeck effect. The thermoelectric generator includes a cavity between the substrate and the thermoelectric elements. The thermoelectric generator includes, within the cavity, a support structure for supporting the thermoelectric elements. The support structure has a thermal conductivity lower than a thermal conductivity of the substrate.

Thermoelectric generator

A method of fabricating a thermoelectric converter that includes providing a layer of a Silicon-based material having a first surface and a second surface, opposite to and separated from the first surface by a Silicon-based material layer thickness; forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first and second thermoelectrically active elements are formed to extend through the Silicon-based material layer thickness, from the first surface to the second surface; forming electrically conductive interconnections in correspondence of the first surface and of the second surface of the layer of Silicon-based material, for electrically interconnecting the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements, and forming an input electrical terminal and an output electrical terminal electrically connected to the electrically conductive interconnections, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material comprise Silicon-based materials selected among porous Silicon or polycrystalline SiGe or polycrystalline Silicon.

Method of fabrication of an integrated thermoelectric converter, and integrated thermoelectric converter thus obtained

A process for manufacturing a micromechanical structure envisages: forming a buried cavity within a body of semiconductor material, separated from a top surface of the body by a first surface layer; and forming an access duct for fluid communication between the buried cavity and an external environment. The method envisages: forming an etching mask on the top surface at a first access area; forming a second surface layer on the top surface and on the etching mask; carrying out an etch such as to remove, in a position corresponding to the first access area, a portion of the second surface layer, and an underlying portion of the first surface layer not covered by the etching mask until the buried cavity is reached, thus forming both the first access duct and a filter element, set between the first access duct and the same buried cavity.

Process for manufacturing a micromechanical structure having a buried area provided with a filter

A method of fabricating a wafer-size photovoltaic cell module includes defining an integrated cellular structure of a light converting monolateral or bilateral junction diode in an epitaxially grown detachable layer including a first deposited metal current collecting terminal of the diode. The method also includes laminating onto the surface of the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions. The method further includes immersing the wafer in a hydrofluoric acid solution causing detachment of the epitaxially grown silicon layer laminated with the film, and polishing the surface of separation of the detached epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a temperature tolerable by the film.

Method of fabrication of plastic film supported single crystal silicon photovoltaic cell structure

A process for forming a final passivation layer over an integrated circuit comprises a step of forming, over a surface of the integrated circuit, a protective film by means of High-Density Plasma Chemical Vapor Deposition.

Process of final passivation of an integrated circuit device

A method for manufacturing a semiconductor device having improved adhesion at an interface between layers of dielectric material, comprising the steps of forming a first layer of dielectric material on at least one part of a structure defined in a semiconductor substrate and forming a second dielectric material layer superimposed on the least one part of the first layer. The method further includes the step of forming, in the part where the first and second layers are superimposed, an intermediate adhesion layer comprising a ternary compound of silicon, oxygen and carbon. The formation of the adhesion layer takes place at low temperature and in an atmosphere kept essentially free of oxidative substances different from those serving to provide the silicon and the carbon to the layer. Preferably the layer is formed by the plasma enhanced chemical vapour deposition technique. The ternary dielectric compound of silicon, oxygen and carbon obtained is preferably useful to aid in adhesion between layers of dielectric materials, particularly in semiconductor devices. Alternatively, in another embodiment of the invention, in a process which is more generally useful for deposition of a dielectric material layer comprising silicon, the layer is formed at low temperature by the chemical vapour deposition technique, preferably plasma enhanced, in an atmosphere kept essentially free of exogenous oxidative substances, (i.e., in which the oxidizer is contained in the molecules used to provide the species of atoms other than oxygen comprised in the layer).

Process for the production of a semiconductor device having better interface adhesion between dielectric layers

A planarization method is disclosed to provide improved protection against cracking of the final passivation layer of integrated circuit devices. In one embodiment, such method includes final passivation of an integrated circuit device including at least one integrated circuit chip. Such final passivation includes the step of forming a layer of protective material over a top surface of the integrated circuit chip, and a subsequent step of planarizing such layer of protective material to obtain a protection layer having a substantially flat top surface.

Method for final passivation of integrated circuit

Process for the production of a semiconductor device having better

A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material, specifically silicon oxynitride or silicon nitride, on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material (silicon oxynitride or silicon nitride particularly) overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2), silicon dioxide in the preferred embodiment, is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

Process for improving the interface union among dielectric materials in

Adhesion between dielectric layers in an integrated circuit

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Agrate Brianza, Italy

Luca Zanotti