Marvell International Limited

Marvell Asia Pte., Ltd.

Luca Vercesi

Fernando De Bernardinis

Davide Visani

Rinaldo Castello

A method for recovering a clock from input data, in a deserializer that couples a transmission medium to receive circuitry of a data transceiver, includes operating, in a first clock recovery loop, on equalized input data from a data recovery loop to provide a first timing error signal, operating, in a second clock recovery loop, on unequalized input data to provide a second timing error signal, combining the first and second timing error signals, and deriving a recovered clock signal from the combined first and second timing error signals using an oscillator circuit. Combining the first and second timing error signals may include operating on the first and second timing error signals in a manner that filters the first timing error signal to remove low-frequency components including adaptation errors introduced by the data recovery loop, and that filters the second timing error signal to remove high frequency components including jitter.

Dual loop for clock recovery in CDR

Embodiments described herein provide an electronic device, which includes a first oscillator configured to output a first clock signal, and a second oscillator that is co-located with the first oscillator on the electronic device. The electronic device further includes a first bandpass filter configured to filter a first input signal derived from the first clock signal received through a negative feedback loop, and to output a first signal component corresponding to the first signal spur. The electronic device further includes a signal reconstruction circuit configured to receive the first signal component and to combine the first signal component into a control signal for the first oscillator, and to feed the control signal combined with the first signal component to the first oscillator to mitigate the first signal spur exhibited in the first clock signal.

Systems and methods for suppressing oscillator-induced spurs in frequency synthesizers

Embodiments described herein include methods and systems for measuring channel impulse responses in a digital communication system. Specifically, statistical properties of the received signals at the receiver of the digital communication system are analyzed to compute, in real time, channel coefficients indicative of the channel state information, which may be time-dependent, without the use of a training signal.

Systems and methods for measuring impulse responses in a digital communication system

An apparatus comprises a plurality of Analog to Digital Converter circuits (ADCs) and a skew detector configured to determine a plurality of indicators corresponding to a plurality of sampling time skews of the plurality of ADCs, respectively. The plurality of ADCs is configured to adjust the plurality of sampling time skews according to the plurality of indicators, respectively. The apparatus is configured to reach an equilibrium state wherein the plurality of indicators are substantially equal. In an embodiment, the apparatus comprises a Time-Interleaved ADC including the plurality of ADCs. A method comprises measuring a plurality of indicators of a plurality of sampling time skews, respectively. The plurality of sampling time skews are associated with a plurality of ADCs, respectively. The plurality of sampling time skews are adjusted according to respective indicators of the plurality of indicators.

Methods for sampling time skew compensation in time-interleaved analog to digital converters

Embodiments of the present disclosure provide system and method for generating a transmission signal. A transmitter generates and transmits a transmission signal based on signal components. Circuitry that is coupled to the transmitter receives complex plane components of a signal to be transmitted and alters the signal such that a complex plane trajectory of the signal passes nearer to an origin of a complex plane of the complex plane trajectory than does an original complex plane trajectory of the signal. The circuitry determines the signal components to be transmitted by the transmitter based on the altered signal.

Avoiding frequency spikes in modulated systems

An apparatus increases the dynamic range of a time to digital converter. The apparatus includes: an input network configured to receive a first signal, a second signal, and a control signal having a sign value; and a time-to-digital converter (TDC) configured to generate a digital code value that represents a time delay value between the first signal and the second signal. The input network is configured to switch where the first signal and second signal are output in response to the sign value that is determined by the time delay value between the first signal and the second signal.

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Pavia, Italy

Luca Vercesi